Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-02-25
2001-05-15
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S096000
Reexamination Certificate
active
06233185
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to burn-in testing at a wafer level of memory integrated circuits such as dynamic random access memory (DRAM) arrays.
BACKGROUND OF THE INVENTION
Semiconductor wafers typically comprise a plurality of substantially isolated “die” or “chips” containing circuitry, separated from each other by scribe line areas. The individual die contained within the wafer are separated by sawing and packaged individually or in multi-chip modules. One common type of integrated circuit die is a dynamic random access memory (DRAM) array.
Not all die on a particular semiconductor wafer are functional; some have manufacturing defects. Certain defects do not reveal themselves immediately after fabrication. For example, an insulating oxide layer between two conductors may be excessively thin in a particular region. Voltage and temperature stress will cause the particular region of excessively thin insulating oxide to break down, resulting in a short circuit between the two conductors which can be detected during electrical testing.
Hence, die must be tested individually to pass functional die and fail nonfunctional die. Testing a die early in the process flow reduces additional expense incurred by further processing, handling, packaging, and testing failing die. For this reason, it is particularly desirable to test integrated circuit die while they are still contained within the wafer, that is, before sawing.
Thus, stressing die prior to testing induces failures in failure-prone die prior to testing. Failing die are detected during testing and discarded. Stress-testing die early in the process flow reduces additional processing, handling, packaging, and testing costs. Burn-in stress testing is often used. By applying elevated power supply voltage levels and heating or cooling die in a chamber, failures are accelerated. Power is supplied to the die for a static burn-in. Power and additional input signals are supplied to exercise the die for a dynamic burn-in. A wafer-level DRAM burn-in technique is desired which induces failure in failure-prone die more fully or quickly.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for stress testing a memory integrated circuit die. A burn-in power supply voltage and a ground voltage are supplied to each memory die of a plurality of memory die on a semiconductor wafer. This burn-in power supply voltage is provided to a cell plate common node of a memory cell storage capacitor. A ground voltage is provided to at least one bit line of a plurality of bit lines. At least one cell access transistor is turned on, thereby allowing conduction between the bit line and a storage node of the memory cell storage capacitor.
A ground voltage is also provided to the common cell plate of the storage capacitor and the burn-in power supply voltage is provided to at least one bit line of the plurality of bit lines. Thus, a burn-in self-stress mode creates stress conditions of differing polarities capable of being coupled across the memory cell storage capacitor dielectric and the cell access transistor. The burn-in self-stress mode also creates stress conditions of differing polarities between at least one bit line of the plurality of bit lines and at least one word line of a plurality of word lines. The burn-in self-stress mode is capable of being conducted during a wafer level burn-in of at least one wafer in a chamber or using equivalent means of heating or cooling the wafer.
In one embodiment, detection of a burn-in power supply voltage at a dedicated pad initiates a burn-in self-stress mode in response. The stress conditions of the burn-in self-stress mode are capable of use in conjunction with an all row high test and a half row high test. In one embodiment, the all row high test places a group of word lines in a binary logic high state, thereby coupling the burn-in self stress conditions of different polarities across memory cell storage capacitor dielectrics. In another embodiment, the all row high test cycles a group of word lines between a binary logic low and a binary logic high, thereby coupling the burn-in self stress conditions of different polarities across memory cell storage capacitor dielectrics. In one embodiment, the half row high test places alternating word lines in a word line sequence at a binary logic high, thereby stressing undesired short circuit conductive paths between adjacent word lines and between storage nodes of adjacent memory cell storage capacitors. In another embodiment, the half row high test cycles alternating word lines in a word line sequence between a binary logic low and a binary logic high, thereby stressing undesired short circuit conductive paths between adjacent word lines and between storage nodes of adjacent memory cell storage capacitors. In one embodiment, the binary logic high voltage is the burn-in power supply voltage.
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Beffa Ray
Cloud Eugene H.
Farnworth Warren M.
Nevill Leland R.
Waller William K.
Fears Terrell W.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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