Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-11-21
2006-11-21
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S113000, C438S614000, C438S613000, C438S717000, C438S616000, C438S128000, C438S637000
Reexamination Certificate
active
07138326
ABSTRACT:
A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
REFERENCES:
patent: 6181569 (2001-01-01), Chakravorty
patent: 6293270 (2001-09-01), Okazaki
Cox Harry D.
Daniel David P.
Gardecki Leonard J.
Gregoritsch, III Albert J.
Keeler Charles H.
Canale Anthony J.
Im Junghwa
International Business Machines Corp.
Lee Eddie
Walsh Robert A.
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