Wafer flow architecture for production wafer processing

Details Wafer flow architecture for production wafer processing Wafer flow architecture for production wafer processing

1993-11-15

1995-12-12

Dang, Thi

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156345, H01L 2100

Patent

active

054746477

ABSTRACT:
A method for controlling the flow of semiconductor wafers within a semiconductor wafer processing facility. This method includes a wafer storage and preparation area (10) and a wafer metrology and etch area (12), both of which are monitored and/or controlled by a master controller (14). The wafer storage and preparation area (10) is typically kept at a class 10 clean room level and is comprised of a wafer storage area (16) and a wafer preparation area (18). The wafer metrology and etch area (12) is typically kept at a class 1000 clean room level and is comprised of an I/O cassette module (22), a wafer pre-aligner (24), a wafer router (26), a wafer metrology instrument (28), and a wafer etching instrument (30). The semiconductor wafers are transported, either manually or automatically, between the wafer storage area (16) and the wafer preparation area (18), as well as between the wafer storage and preparation area (10) and the wafer metrology and etch area (12), within wafer storage cassettes ( 20). The semiconductor wafers are individually transported between the I/O cassette module (22), the wafer pre-aligner (24), the wafer metrology instrument (28), and the wafer etching instrument (30) by the wafer router (26).

REFERENCES:
patent: 5176783 (1993-01-01), Yoshikawa
patent: 5246524 (1993-09-01), Kuroda et al.
patent: 5291415 (1994-03-01), Zarowin et al.

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