Wafer flatness evaluation method, wafer flatness evaluation...

Details Wafer flatness evaluation method, wafer flatness evaluation... Wafer flatness evaluation method, wafer flatness evaluation...

2007-06-12

2007-06-12

Kim, Peter B. (Department: 2851)

Photocopying

Projection printing and copying cameras

Detailed holder for photosensitive paper

C355S053000

Reexamination Certificate

active

10739275

ABSTRACT:
There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

REFERENCES:
patent: 2002/0008864 (2002-01-01), Kondo
patent: 2003/0023402 (2003-01-01), Kobayashi et al.
patent: 2000 146569 (2000-05-01), None
patent: WO 02/41380 (2001-11-01), None
Fujisawa, T. et al. “Analysis of Wafer Flatness for CD Control in Photolithography”, Optical Microlithography XV, Proceedings of SPIE, vol. 4691, pp. 802-809 (Mar. 2002).
“Technical Programs for the Semiconductor and Flat Panel Display Equipment and Materials Industries”, Semi Japan Silicon Wafer Workshop, pp. 101-106, (2001).
Fukuda, T., JEITA Flatness Study IV and the Impact of Edge Roll-off on CMP, Advanced Wafer Geometry Task Force 2002 SEMICON/Europe, 23 pages, Apr. 17, 2002.
Official Action from the State Intellectual Property Office of the People's Republic of China dated Aug. 12, 2005, and English language translation of same.

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