Radiant energy – Inspection of solids or liquids by charged particles – Analyte supports
Reexamination Certificate
2002-07-29
2003-12-16
Lee, John R. (Department: 2881)
Radiant energy
Inspection of solids or liquids by charged particles
Analyte supports
C355S072000, C355S073000
Reexamination Certificate
active
06664549
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a wafer chuck and an exposure technique which use the wafer chuck, and to a manufacturing technique of semiconductor device and, more particularly, to a technique which is effectively applied to a wafer chuck or the like used for vacuum-chucking a semiconductor wafer in the steps in manufacturing a semiconductor device.
BACKGROUND ART
For example, in an exposure system which coats a resist on a semiconductor wafer and which exposes and develops a circuit pattern of one layer formed on a reticle serving as an original so as to form a predetermined resist pattern on the semiconductor wafer, the degree of flatness of the semiconductor wafer is an important technical object in order to prevent resolving defects caused by not obtaining an image formation within a focal depth and to form a sharp circuit pattern. For this reason, a flat state of the semiconductor wafer is to be required by such a way that the wafer is vacuum-chucked from the rear surface thereof by a wafer chuck having a high degree of flatness. An exposure process is performed to the wafer.
As an example in which such an exposure system is described in detail, “VLSI MANUFACTURING AND TEST DEVICE GUIDEBOOK IN 1998” issued by Kogyo Chosakai Publishing Co., Ltd. (Nov. 20, 1997) is known. The wafer chuck has a configuration in which a large number of support pins are implanted inside a cap-like vessel. However, in this structure, the outer peripheral wall of the cup-like vessel and the large number of support pins are brought into contact with the rear surface of the semiconductor wafer so as to apply the negative pressure into the cap-like vessel, thereby supporting the semiconductor wafer. Therefore, warpage of the peripheral portion of the semiconductor wafer is not sufficiently corrected. Since micropatterning in a process makes the focal depth further small, flattening a semiconductor wafer in exposure becomes an important technical object every year.
With respect to the art, as an important which increases the degree of flatness in the peripheral portion of a semiconductor wafer, an art disclosed in Japanese Patent Application Laid-Open No. 8-37227 is known. This art can achieve a predetermined effect such an in correction of upward warping transformation at the peripheral portion of the semiconductor wafer.
SUMMARY OF THE INVENTION
However, in the wafer chuck described in the above conventional art, a sufficient degree of flatness cannot be achieved. More specifically, when a wafer is warped reversely (downwardly) in the above invention, the invention does not disclose a predetermined relationship in shape which corrects the warpage so that wafer correction for realizing a high degree of flatness in the entire area of the semiconductor wafer has a given limit.
It is an object of the present invention to provide a technique which can more effectively prevent warpage of a semiconductor wafer vacuum-chucked on a wafer check and which can realize a high degree of flatness of the entire area of the semiconductor wafer.
It is another object of the present invention to provide a technique which can vacuum-chuck semiconductor wafers having various diameters on single wafer chuck.
It is still another object of the present invention to provide a technique which can improve the manufacturing yield of semiconductor devices.
The above objects and other objects of the present invention and novel characteristic features will be apparent from the description of this specification and the accompanying drawings.
The outline of typical one of the aspects of the present invention will be briefly described below.
More specifically, a wafer chuck according to the present invention is adopted to flatly vacuum-chucks a semiconductor wafer having a rear surface which is held on support pins by suction with a suction chamber at a negative pressure applied thereto, the suction chamber surrounded by an external wall, wherein the upper surface of the external wall is formed to have a level slightly lower than those of the upper surfaces of the support pins; the external wall does not chuck the semiconductor wafer and does not in contact with the semiconductor wafer; and air is slightly sucked into the suction chamber.
In addition, the wafer chuck is characterized in that the distance between the external wall and the closest support pin is kept constant, a moment is generated such that the gradient of the semiconductor wafer being in contact with the outermost closest support pin is small, and flexure of the semiconductor wafer caused by vacuum is minimum.
An exposure system according to the present invention is characterized by being constituted by using the wafer chuck.
A method of manufacturing a semiconductor device according to the present invention applies the wafer chuck to the step of polishing a semiconductor wafer and an exposure system for exposing the semiconductor wafer to manufacture a semiconductor device.
According to the wafer chuck having the above constitution, inflow air generates a pressure loss by the external wall to make the pressure in the suction chamber negative, a vacuum pressure between the external wall and the closest support pin is generated by the negative pressure. When a moment generated by the vacuum pressure is equal to moment acting on the internal side of the closest support pin, the wafer is not inclined at a position above the closest support pin because the moments are balanced.
In addition, when the distance between the external wall and the closest support pin is not more than a predetermined distance, flexure or gradient of the wafer from the closest support pin to an external bank can be made sufficiently small. For this reason, the degree of flatness of the wafer near the peripheral portion of the wafer can be maintained at high accuracy.
According to the exposure system using the wafer chuck described above, even in a micropatterning process having a small focal depth, a preferable circuit pattern can be transferred to a semiconductor wafer.
According to the method of manufacturing a semiconductor using the wafer chuck or the exposure system, a semiconductor device can be manufactured even in a micropatterning process having a small focal depth.
REFERENCES:
patent: 5923408 (1999-07-01), Takabayashi
patent: 6307620 (2001-10-01), Takabayashi et al.
patent: 6461980 (2002-10-01), Cheung et al.
patent: 6563586 (2003-05-01), Stanke et al.
patent: 03163848 (1991-07-01), None
patent: 08037227 (1996-02-01), None
patent: 08195428 (1996-07-01), None
patent: 10242255 (1998-09-01), None
patent: 2001185607 (2001-07-01), None
“VLSI Manufacturing and Test Device Guidebook in 1998” issued by Kogyo Chosakai Publishing Co., Ltd. Japan, (Nov. 20, 1997), p. 56, which is cited in the Specification.
Honda Teruo
Kobayashi Seiichiro
Koyanagi Koichi
Motohashi Masaharu
Saeki Hideo
Gurzo Paul M.
Hitachi Tokyo Electronics Co. Ltd.
Lee John R.
McCormick Paulding & Huber LLP
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