Wafer burn-in test mode circuit

Details Wafer burn-in test mode circuit Wafer burn-in test mode circuit

2006-02-07

2006-02-07

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06996753

ABSTRACT:
A wafer burn-in test mode circuit includes a command decoder, an address latch circuit configured to latch an address signals, a register configured to store a wafer burn-in address signal from the address latch, a wafer burn-in test mode entry circuit configured to generate a wafer burn-in test mode entry signal according to the wafer burn-in address signal and a command signal from the command decoder, a shift registers configured to shift the wafer burn-in address signal according to the wafer burn-in test mode entry signal and a wafer burn-in clock signal, a wafer burn-in test priority decision circuit configured to output test priority signals according to output signals of the shift registers, and a decoder configured to decode the output signals of the shift registers according to the priority signals and configured to output wafer burn-in test signals corresponding to a wafer burn-in test item.

REFERENCES:
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patent: 5617531 (1997-04-01), Crouch et al.
patent: 6233184 (2001-05-01), Barth et al.
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patent: 6341089 (2002-01-01), Sawada et al.
patent: 6400173 (2002-06-01), Shimizu et al.
patent: 6414890 (2002-07-01), Arimoto et al.
patent: 6490223 (2002-12-01), Han et al.
patent: 2002/0021603 (2002-02-01), Lim et al.

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