Wafer burn-in test circuit of a semiconductor memory device

Details Wafer burn-in test circuit of a semiconductor memory device Wafer burn-in test circuit of a semiconductor memory device

1997-11-05

1999-08-10

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36523006, 365191, G11C 700

Patent

active

059368993

ABSTRACT:
A wafer burn-in test circuit of a semiconductor memory device which can provide a burn-in stress voltage by only using a prior word line driver without additional devices or circuits. The wafer burn-in test circuit of the present invention comprises a row address pre-decoding circuit for selecting and driving a predetermined word line by a combination composed of row address signals, a word line driving control circuit for outputting a first signal to selectively drive the word line when at least one signal among address signals pre-decoded by the row address pre-decoding circuit is enabled, and outputting a second signal to enable the all word lines with no relation to a logic status of the address signals when a wafer burn-in signal is inputted, and a row decoder circuit for receiving output signals provided from the row address pre-decoding circuit and the word line driving control circuit therein, and for selectively driving the word line by the address signal in a normal mode of operation and simultaneously driving a plurality of word lines in a wafer burn-in mode of operation.

REFERENCES:
patent: 5265057 (1993-11-01), Furuyama et al.
patent: 5282167 (1994-01-01), Tanaka et al.
patent: 5381373 (1995-01-01), Ohsawa
patent: 5544123 (1996-08-01), Hoshi et al.
patent: 5590079 (1996-12-01), Lee et al.

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