Wafer burn-in circuit for a semiconductor memory device

Static information storage and retrieval – Read/write circuit – Testing

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365200, 365203, G11C 700

Patent

active

059264233

ABSTRACT:
A wafer burn-in circuit for a semiconductor memory device which can detect defected cells in an early stage and increase a yield by applying a stress to bit lines in a wafer state to detect the defected cells and repair the same according to the present invention, is disclosed. To this end, a wafer burn-in circuit for a semiconductor memory device according to the invention includes an equalizing means for bit line for equalizing said bit lines at a standby operation stage, wherein the equalizing means for bit line is controlled by a first precharge signal for bit line. A stress inputting means for bit line is provided to input a stress voltage to the bit lines at a wafer burn-in operation stage, wherein the stress inputting means for bit line is controlled by a second precharge signal for bit line. A stress transferring means for bit line is also provided to make its output to be in a floating state at an normal operation stage, whereas it outputs a stress voltage to the stress inputting means for bit lines at the wafer burn-in operation stage.

REFERENCES:
patent: 5255229 (1993-10-01), Tanaka et al.
patent: 5357193 (1994-10-01), Tanaka et al.
patent: 5657282 (1997-08-01), Lee

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