Wafer bumping process

Details Wafer bumping process Wafer bumping process

2005-07-26

2005-07-26

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S614000, C257S737000, C257S780000

Reexamination Certificate

active

06921716

ABSTRACT:
A wafer bumping process is disclosed. A wafer having a plurality of bonding pads formed thereon is provided. A first under bump metallurgy layer is formed to cover the bonding pads. A first patterned photoresist layer having a plurality of first openings is formed on the first under bump metallurgy layer, wherein a portion of the first under bump metallurgy layer is exposed within the first openings. A second under bump metallurgy layer is formed within the first openings, wherein the second under bump metallurgy layer is much thicker than the first under bump metallurgy layer. A second patterned photoresist layer having a plurality of second openings is formed on the first patterned photoresist layer, wherein the second openings being larger than the first openings. After filling the second openings with a solder material, a reflowing process is performed to form a plurality of solder bumps, wherein the material of the second under bump metallurgy layer has a melting point higher than that of the solder material.

REFERENCES:
patent: 6229220 (2001-05-01), Saitoh et al.
patent: 6372622 (2002-04-01), Tan et al.
patent: 6750133 (2004-06-01), Datta
patent: 6784087 (2004-08-01), Lee et al.

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