Metal treatment – Barrier layer stock material – p-n type – With recess – void – dislocation – grain boundaries or channel...
Patent
1986-02-19
1988-11-08
Chaudhuri, Olik
Metal treatment
Barrier layer stock material, p-n type
With recess, void, dislocation, grain boundaries or channel...
437249, 437225, 357 55, H01L 2102, H01L 2906
Patent
active
047832258
ABSTRACT:
A wafer having chamfered bent portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer such as an orientation flatness. The chipping of the wafer can be prevented, and in coating the wafer with a photoresist, forming an epitaxially grown layer on the wafer, etc., films having desired characteristics can be provided on the surface of the wafer.
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patent: 3951728 (1976-04-01), Egashira et al.
patent: 4228937 (1980-10-01), Tocci
patent: 4256229 (1981-03-01), Lee
patent: 4344260 (1982-08-01), Ogiwara
patent: 4488930 (1984-12-01), Koe
"Silicon Wafers with Optimum Edge Rounding," Solid State Technology, pp. 16-17, May 1976.
Semiconductor Silicon Manufacturing and Machining Using Diamond Tools-G. Janus, Burghausen.
IBM Tecnical Disclosure Bulletin, vol. 22, No. 3 "Diagnostic Method for Locating the Wafer Position in a Crystal".
IBM Technical Disclosure Bulletin, vol. 11, No. 12, "Diffusion Boat".
Egashira Etuo
Komoriya Susumu
Maejima Hisashi
Nishizuka Hiroshi
Chaudhuri Olik
Hitachi , Ltd.
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