Wafer alignment mark utilizing parallel grooves and process

Details Wafer alignment mark utilizing parallel grooves and process Wafer alignment mark utilizing parallel grooves and process

1990-05-15

1992-04-21

Hearn, Brian E.

Metal treatment

Barrier layer stock material, p-n type

With recess, void, dislocation, grain boundaries or channel...

148DIG102, 437924, H01L 2934

Patent

active

051064324

ABSTRACT:
A wafer alignment mark consists of patterns, such as a chevron and two stripes, formed in the surface of a semiconductor wafer. Each pattern is defined by a pair of parallel grooves, separation between all pairs of grooves being the same. Each groove provides one sharp edge which can be reliably detected by an automatic alignment system.
A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges.

REFERENCES:
patent: 3796497 (1974-03-01), Mathisen et al.
patent: 4200395 (1980-04-01), Smith et al.

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