Wafer acceptance testing method and structure of a test key...

Details Wafer acceptance testing method and structure of a test key... Wafer acceptance testing method and structure of a test key...

2005-06-14

2005-06-14

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C257S048000

Reexamination Certificate

active

06905897

ABSTRACT:
A wafer acceptance testing method for monitoring GC-DT misalignment and a test key structure are disclosed. The test key includes a deep trench capacitor structure biased to a first voltage (VDT). The deep trench capacitor structure includes a buried strap out diffusion region A GC-T electrode layout, which is biased to a second voltage (VGC-T), includes a plurality of columns of GC-T fingers. A GC-B electrode layout, which is biased to a third voltage (VGC-B), includes a plurality of columns of GC-B fingers that interdigitate the GC-T fingers. A first capacitance C1of a first capacitor contributed by the GC-T fingers and the buried strap out diffusion region is measured. A second capacitance C2of a second capacitor contributed by the GC-B fingers and the buried strap out diffusion region is measured. The first capacitance C1and second capacitance C2are compared, wherein when C1≠C2, GC-DT is misaligned.

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