Voting circuit and method

Details Voting circuit and method Voting circuit and method

1998-12-15

2000-09-12

Tokar, Michael

Electronic digital logic circuitry

Threshold

326 11, 327 63, 714797, H03K 1923

Patent

active

061182974

ABSTRACT:
A voting circuit (34) comprises a first variable delay (60) operable to receive a first set of signals in a clock signal and to determine a first delay based on the first set of signals. The first variable delay (60) generates a first delayed output in response to the first delay of the clock signal. A second variable delay (62) is operable to receive a second set of signals and a clock signal and to determine a second delay based on the second set of signals. The second variable delay (62) generates a second delayed output in response to the second delay of the clock signal. A latch (64) is connected to the first and second variable delays. The latch (64) is operable to receive the first and second delayed outputs and to generate a latched voting output in response to at least one of the first and second delayed outputs.

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patent: 5784386 (1998-07-01), Norris
patent: 5838166 (1998-11-01), Nakamura

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