Voltage withstanding structure for a semiconductor device

Details Voltage withstanding structure for a semiconductor device Voltage withstanding structure for a semiconductor device

2000-01-31

2003-08-05

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

Field relief electrode

C257S489000, C257S491000, C257S492000

Reexamination Certificate

active

06603185

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a planar horizontal type and a planar vertical type semiconductor device, and particularly to a voltage withstanding structure therefor.
2. Description of the Related Art
Power devices represented by a bipolar transistor, a power MOSFET and IGBT (Insulated Gate Bipolar Transistor) requires a voltage withstanding structure (i.e. structure of an area having a withstand voltage) of several tens to several thousands volts. In order to drive these power devices, in recent years, many attempts have been made to develop a high withstand voltage IC. The high withstand voltage IC also requires a withstand voltage substantially equal to the requirement for the power device.
FIGS. 10A and 10B
show a composite structure of a Double RESURF structure and a resistive field plate structure.
FIG. 10A
is a sectional view of the main portion thereof and
FIG. 10B
is a graph of a potential distribution thereof. This voltage withstanding structure is a typical high withstand voltage IC.
As seen from
FIG. 10A
, an N-well region
34
is formed in a surface layer of a p-type substrate
35
. In a surface layer of this N-well region
34
, a high potential region
33
, a low potential region
37
and P-offset region
39
are formed. On the high potential region
33
and low potential region
37
, a high potential side electrode
32
and a low potential side electrode
38
are formed, respectively. On the dielectric oxide film
41
formed on the p-type substrate
35
, a thin film resistive layer
40
is formed which is a resistive field plate having high resistivity. This thin film resistive layer
40
makes an electric contact between the high potential side electrode
32
and low potential side electrode
38
. The low potential side electrode
38
is electrically connected to the electrode
36
on the rear side at an end portion of the p-type substrate
35
. Reference numeral
35
a
denotes a p-type substrate layer.
FIG. 10B
shows the state of the potential distribution on the chip surface when a high potential Vs is applied to the high potential side electrode
32
with respect to the low potential side electrode
38
(e.g. GND).
The potential distribution has a great distortion at the vicinity of both ends of the resistive field plate
40
where an electric field is concentrated. Accordingly, the withstand voltage is lowered at these portions.
FIG. 11
is a view showing the enlargement of a depletion layer within a semiconductor. The sectional view of the main portion of a semiconductor device shown in
FIG. 11
is the same as that shown in FIG.
10
A. Therefore, reference numerals in
FIG. 11
refer to the same as the reference numerals in FIG.
10
A.
In
FIG. 11
, when the a positive potential Vs is applied to the high potential side electrode
32
with respect to the low potential side electrode
38
and the rear side electrode
36
, depletion layers
47
and
48
expand from two p-n junctions which are reverse-biased.
One p-n junction is formed between the N-well region
34
and P-offset region
39
or low potential region
37
, and another p-n junction is formed between the N-well region
34
and p-type substrate layer
35
a.
Generally, because of influence of fixed charge at the boundary between the dielectric oxide film
41
and semiconductor, an electric field is liable to concentrate within the depletion layer on the semiconductor surface, which leads to breakdown of the device.
In the resistive field plate structure, when a potential Vs is applied to the high potential side electrode
32
, the potential Vs is also applied to the thin film resistive layer
40
so that a current corresponding to the potential Vs and the resistance of the thin film resistive layer
40
flows through the thin film resistive layer
40
. Thus, if a uniform potential distribution is generated in the thin film resistive layer
40
, the electric field due to this potential distribution affects the semiconductor layer so that the concentration of the electric field within the depletion layer on the surface of the semiconductor layer can be relaxed. This assures the high withstand voltage stably.
In the conventional structure, in order that a large leak current is not generated between the high potential region
33
and low potential region
37
, as the thin film resistive layer
40
which is a field plate, a layer having high resistivity of several M&OHgr; cm, e.g. of non-doped amorphous silicon or oxygen-doped polysilicon (SIPOS) has been adopted.
However, in order to form the high-resistivity layer of several M&OHgr; cm surely, the impurities invading this layer have to be restricted to a very small quantity, thereby making it difficult to manufacture the device. The value of the resistivity is likely to vary according to positions.
Where the resistance of the thin film resistive layer
40
is low, the variation of the resistance is small. However, because a large leak current flows, a large loss occurs. This lead to breakdown of the device. On the other hand, the resistance of the thin film resistive layer
40
is too high, a variation of the resistance is generated so that the leak current is likely to flow non-uniformly. This makes it difficult to form a uniform electric potential distribution between the high potential region
33
and low potential region
37
. This produces an area where the electric field concentrates within the depletion layer of the semiconductor layer. Because of this, a withstand voltage may be lowered.
A proposal for solving these problems is disclosed in JP-A-4-332173 in which, as shown in
FIG. 12
, the resistance of the thin film resistive layer
40
is reduced to restrict its variation, and the thin film resistive layer
40
is formed in a spiral shape between an island base electrode
43
(high potential side electrode) and a peripheral electrode
44
(low potential side electrode) encircling it so that this long thin film resistive layer (spiral thin film resistive layer
45
) connects the base electrode
43
to the peripheral electrode
44
, thereby increasing the resistance.
In this structure, the resistivity of the spiral thin film resistive layer
45
is reduced to restrict its variation, and the resistance from end to end of the spiral thin film resistive layer
45
is increased to suppress the leak current. The potential distribution on the segment connecting the base electrode
43
and peripheral electrode
44
in line changes stepwise by the number of times of spiral winding of the spiral thin film resistive layer
45
. An increase of the number of times of winding decreases a drop between the steps, thereby making the average potential gradient constant.
The structure described above realizes, as a lower value, the resistivity of the spiral resistive layer
45
electrically connecting the peripheral electrode
44
and base electrode
43
than that of the resistive field plate having the conventional structure. This structure has an advantage of capable of easily controlling the resistivity as compared with the case of the field plate.
However, an increase in the chip size of a semiconductor device when the spiral thin film resistive layer
45
is formed lengthens the length of the spiral thin film resistive layer
45
so that its resistance becomes large. In order to cause the equal leak current to flow irrespectively of the chip size, when the chip size is increased, the width of the spiral thin film resistive layer
45
must be extended. This necessarily increases the width of the voltage withstanding structure arranged in the periphery. Therefore, with the semiconductor device having the same withstand voltage, the width of the voltage withstanding structure must be changed according to its current capacity, i.e. area of an active region. This is inconvenient in production cost when the semiconductor devices in the same withstand voltage series are produced.
Although the value of the resistivity of the thin film adopted as the spiral thin film resistive layer has become settable as a

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