Voltage variation compensation arrangement for sample and hold c

Details Voltage variation compensation arrangement for sample and hold c Voltage variation compensation arrangement for sample and hold c

1994-03-28

1995-05-09

Blum, Theodore M.

Electric lamp and discharge devices: systems

Cathode ray tube circuits

Cathode-ray deflections circuits

348746, H01J 2951

Patent

active

054143292

ABSTRACT:
An analog multiplier generates an output signal that is coupled to a convergence winding of a projection television. The analog multiplier multiplies a horizontal rate sawtooth signal with a vertical rate parabola signal. The multiplier DC operating point is adjusted, by developing a DC voltage in a hold capacitor of a sample and hold arrangement during each vertical blanking interval. To prevent a change in the capacitor voltage during vertical trace, a vertical rate sawtooth signal is coupled to the hold capacitor via a second capacitor.

REFERENCES:
patent: 4500816 (1985-02-01), Murphy
patent: 4634937 (1987-01-01), Haferl
patent: 4709193 (1987-11-01), Dietz
Appln. Ser. No. 08/115,602, filed Sep. 3, 1993 in the name of J. B. George, entitled Automatic Calibration in a Waveform Generator for Deflection.
Analog-Digital Coversion Handbook, pp. III-73--III-86.

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