Voltage variable capacitor with improved C-V linearity

Details Voltage variable capacitor with improved C-V linearity Voltage variable capacitor with improved C-V linearity

1999-12-29

2001-08-21

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S595000, C257S295000, C257S310000

Reexamination Certificate

active

06278158

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to voltage variable capacitors with improved C-V linearity and to methods of fabricating the improved voltage variable capacitors.
BACKGROUND OF THE INVENTION
As is known in the art, voltage variable capacitors (VVC) are formed using standard semiconductor processes and techniques. In general, a semiconductive layer is formed on a semiconductor substrate by forming a doped layer on the surface of the substrate. An insulating layer is then formed on the surface of the doped layer and a pair of RF capacitors are formed by depositing two spaced apart metal contacts on the surface of the insulating layer. Each contact forms a capacitor in conjunction with the underlying semiconductive layer. The two spaced apart metal contacts are I/O contacts for the VVC and opposite contacts for each of the capacitors are connected together and to the back side of the substrate by the semiconductive layer.
The VVC is connected into a circuit by connecting a first variable DC voltage between the back side of the substrate and one of the two spaced apart metal contacts and a second variable DC voltage between the back side of the substrate and the other of the two spaced apart metal contacts. Generally, the two variable voltages are the same and are supplied by one voltage supply. The VVC has a typical S-shaped capacitor-voltage (C-V) waveform. The problem is that the C-V waveform has breaks or very sharp corners (i.e. C
min
and C
max
) in it which produce irregularities in the inter-modulation (IM) performance. Also the linear portion of the curve (between Cmin and Cmax) is relatively short which reduces the linearity of the VVC. Additionally, the electrical connection to the back side of the semiconductor substrate causes connection difficulties in some applications, e.g. flip chip applications and the like. Also, the need to provide an electrical contact on the back side of the substrate causes additional process steps and cost in the fabrication.
Accordingly it is highly desirable to provide apparatus which overcomes or reduces these problems and an improved method of fabrication.


REFERENCES:
patent: 5965912 (1999-10-01), Stolfa et al.
patent: 6072208 (2000-06-01), Nishihara
patent: 6172378 (2001-01-01), Hull et al.

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