Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2000-06-21
2002-07-23
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S074000, C326S063000
Reexamination Certificate
active
06424173
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to logic circuits and voltage translators. More particularly, it relates to a novel class of logic translators that consume zero static power and provides predictable performance.
BACKGROUND ART
Differential Arm Electronics IC (AE) designed for disk drives require a number of novel circuits due to the pre-amp architecture chosen and the voltage limitations imposed by the silicon technology. For instance, an AE chip is required to have its integrated circuit (IC) substrate connected to the most negative voltage present on the chip, which is typically −4 V. The silicon technology further dictates that the terminal voltage not exceed 5 V between any two terminals (amongst Source, Drain, Gate, and Body) of a field-effect-transistor (FET) fabricated on the chip. Hence, voltage translators are incorporated in AE to mitigate the above limitations.
Although various voltage translators are used in the art for shifting logic levels and other applications, as exemplified by U.S. Pat. Nos. 5,818,278, 5,506,535, 5,420,527, 4,625,129, and 4,321,491, these prior art voltage translators either do not shift an input logic level below ground to a negative output level, or consume non-zero static power. Another drawback of the prior art devices is that the output level often becomes unstable and ill-defined when the on-chip power supply is transitionally invalid (e.g., when it is initially turned on/off).
What is needed in the art, therefore, are voltage translators that can shift down or up an input logic level, while consuming zero static power and providing predictable performance.
OBJECTS AND ADVANTAGES
Accordingly it is a principal object of the present invention to provide a novel class of voltage translators that translate a set of input logic levels (e.g., Low=0 V and High=5 V) to another set of output logic levels (e.g., Low=−4 V and High=0 V), and vice versa, and consume no static power. It is another object of the present invention to provide voltage translators that operate reliably and predictably.
A notable feature of the voltage translators of the present invention is that they are simple in design, yet versatile and reliable in performance. Another important advantage of the voltage translators of the present invention is that they are composed of all CMOS devices (i.e., no bipolar transistors, no resistors, etc., are used), and consume no static power. Moreover, the voltage translators of the present invention can be easily adapted to a variety of applications.
These and other objects and advantages will become apparent from the following description and accompanying drawings.
SUMMARY OF THE INVENTION
This invention presents a voltage translator, including an input stage and a translation stage, all made of CMOS-devices. The input stage receives an input logic level and generates first and second complementary levels. The complementary levels are then fed to the translation stage, which generates an output logic level that is either shifted up, or shifted down, with respect to the input logic level.
The input stage can be as simple as an inverter, preferably a CMOS inverter. In this case, the original input logic level provides the first complementary level, while the output of the inverter, which is inverted with respect to the input logic level, is used as the second complementary level. There may be any number of additional inverters cascaded to follow the first inverter, acting as a buffer to provide an isolation between the input and translation stages.
The translation stage includes a plurality of CMOS p-channel field-effect-transistor (PFET) and n-channel field-effect-transistor (NFET), coupled to a latch. The translation stage receives the first and second complimentary levels from the input stage and generates an output logic level, which is shifted either up or down with respect to the input logic level. The translation stage may further include a pre-set stage. The presence of the latch enables the circuit to hold the output level at a predetermined value when the power supply is transitionally invalid (e.g., when the circuit is shutting off). The function of the pre-set stage is to initialize the latch when the circuit is turned on.
The voltage translators of the present invention can translate a set of input logic levels (0, 5 V) to a set of output logic levels (−4 V, 0), and vice versa. They are designed such that no static power is consumed. Furthermore, the latch action employed in these voltage translators makes the output level predictable and stable, even as the power supply decays during power-off.
The novel features of this invention, as well as the invention itself, will be best understood from the following drawings and detailed description.
REFERENCES:
patent: 4321491 (1982-03-01), Atherton et al.
patent: 4625129 (1986-11-01), Ueno
patent: 5087841 (1992-02-01), Rogers
patent: 5276362 (1994-01-01), Obregon et al.
patent: 5420527 (1995-05-01), Naber
patent: 5506535 (1996-04-01), Ratner
patent: 5818278 (1998-10-01), Yamamoto et al.
Chang Daniel D.
Tokar Michael
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