Voltage translator with data buffer

Details Voltage translator with data buffer Voltage translator with data buffer

2006-09-05

2006-09-05

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S082000, C326S080000

Reexamination Certificate

active

07102389

ABSTRACT:
A voltage translator with data buffer includes an input inverter receiving a data input signal at a first voltage level. A level shifting cross-coupled NOR circuit is coupled to the input inverter for translating the data input signal at a second voltage level. An output stage driven by the level shifting cross-coupled NOR circuit for providing a data output signal at the second voltage level. The voltage translator enables improved performance across various power, voltage and temperature (PVT) conditions and reliably reduces or minimizes shoot through current and delay.

REFERENCES:
patent: 5126588 (1992-06-01), Reichmeyer et al.
patent: 5272481 (1993-12-01), Sauer
patent: 5760621 (1998-06-01), Keeth
patent: 5999033 (1999-12-01), Keeth et al.
patent: 6127849 (2000-10-01), Walker
Michael Lewis, 1999 Online reference for Fig 1, 2: http://www.geocities.com/cmoslayoutdesign/gmask/gmask04.html.

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