Voltage translator circuit and semiconductor memory device

Details Voltage translator circuit and semiconductor memory device Voltage translator circuit and semiconductor memory device

2008-01-08

2008-01-08

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S087000

Reexamination Certificate

active

07317334

ABSTRACT:
A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder110is changed from the potential GND to the potential VDD, a pMOS transistor125is turned off, and the gate of nMOS transistor124comes to have a high impedance. Because of this, the self-boost effect acts on the gate of the nMOS transistor124to push up the source potential of the nMOS transistor124. Consequently, the gate potential of the pMOS transistor122is abruptly raised, and this pMOS transistor122is turned off at high speed. The pMOS transistor122being turned off at high speed, the penetration current flowing through the transistors121and122is reduced and the electric potential of the word line WL falls at high speed. This voltage translator circuit can be achieved only by adding a low voltage pMOS transistor125to the prior art voltage translator circuit, thus enabling the circuit area of the voltage translator circuit to make smaller.

REFERENCES:
patent: 4931670 (1990-06-01), Ting
patent: 5764077 (1998-06-01), Andresen et al.
patent: 829881 (1998-03-01), None

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