Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1998-03-26
2000-05-16
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 68, 326 86, H03K 190185
Patent
active
060642297
ABSTRACT:
An integrated circuit, voltage translating buffer includes input, intermediate and output circuit stages. Each, circuit stage includes first and second n-FETS and a p-FET connected in series. The first n-FET of the input stage receives a first logic voltage within a low voltage range at its gate terminal. The output stage provides a translated output voltage within a higher voltage range at a circuit node between the second n-FET and the p-FET. Each of the second n-FETS of the three stages is operable to drop sufficient voltage across its conducting channel so as to prevent an excessive voltage drop across the conducting channel of the associated series connected first n-FET. Consequently, low voltage transistors may be used for the n-FETS, such that the buffer circuit can be manufactured with a reduced number of mask levels.
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patent: 5440249 (1995-08-01), Schucker et al.
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patent: 5808480 (1998-09-01), Morris
patent: 5834948 (1998-11-01), Yoshizaki et al.
patent: 5892371 (1999-04-01), Maley
Lucent Technologies - Inc.
Santamauro Jon
LandOfFree
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