Voltage tolerant input/output buffer

Details Voltage tolerant input/output buffer Voltage tolerant input/output buffer

1997-02-19

1999-05-25

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 27, 326 86, H03K 190185

Patent

active

059072490

ABSTRACT:
A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit. The current mirror and the voltage sensing and isolating circuit are provided such that as the higher voltage circuit applies a high supply voltage to the drain of the pull-up output transistor, the pull-up output transistor is able to transition to a state at the supply voltage of the lower circuit and sink the current such that the buffer operates properly and correctly, unaffected by the application of the higher operating supply voltage to the drain of the pull-up transistor.

REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5381062 (1995-01-01), Morris
patent: 5424659 (1995-06-01), Stephen et al.
patent: 5512844 (1996-04-01), Nakakura et al.
patent: 5576635 (1996-11-01), Partovi et al.
patent: 5635861 (1997-06-01), Chan et al.
Brian Henderson and Laszlo Gal, 5 V Compatibility With 3.3 V-Only CMOS ASICs, Microelectronics Journal, vol. 23, No. 8, 1992, (pp. 577-580).
Nora Maene, et al., On Chip Electrostatic Discharge Protections For Inputs, Outputs and Supplies of CMOS Circuits; EOS/ESD Symposium 92-231, date unknown, (pp. 5B.1.1-5B.1.6).
Marcel J. M. Pelgrom and E. Carel Dijkmans, A 3/5V Compatible I/O Buffer; IEEE Journal of Solid-State Circuits, vol. 30, No. 7, Jul. 7, 1995, (pp. 823-825).
Makoto Takahashi, et al. 3.3V-5V Compatible I/O Circuit Without Thick Gate Oxide, IEEE 1992 Custom Integrated Circuits Conference, 1992, (pp. 23.3.1-23.3.4).
Steven H. Voldman, ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50- and 0.25 .mu.m Channel Length CMOS Technologies, EOS/ESD Symposium 94-125, date unknown, (pp. 3.4.1-3.4.10).

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