Voltage tolerant input buffer

Electronic digital logic circuitry – Interface – Supply voltage level shifting

Reexamination Certificate

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Details

C326S082000, C326S083000, C326S084000

Reexamination Certificate

active

10940161

ABSTRACT:
A method and an apparatus are described for a voltage tolerant input buffer. An embodiment of an input buffer includes a differential circuit and a plurality of switches coupled with the differential circuit. The plurality of switches applies a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state.

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EIA/JEDEC Standard—Aug. 1995—Electronic Industries Association High speed transceiver logic (hstl) a 1.5 v output buffer supply voltage based interface standard for digital integrated circuits.

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