Voltage tolerant buffer

Details Voltage tolerant buffer Voltage tolerant buffer

1997-11-19

2001-03-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S080000

Reexamination Certificate

active

06208167

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to circuits made using transistors, and particularly to buffers made using transistors for coupling a circuit operating at a low voltage to a circuit operating at a high voltage, or vice versa.
2. Description of the Related Art
There is a continuing need in the art of electronics to increase the number and decrease the size of transistors in integrated circuit (IC) chips to obtain greater complexity, functionality, computational power, and performance speed. There is also a continuing need to reduce the power consumed by IC chips due to increases in the number of transistors fabricated on such IC chips, and due to market demands for highly reliable and battery operated integrated circuitry. These various needs have prompted the development of mixed voltage integrated circuitry, wherein a circuit operating at a low voltage (LV
DD
) is coupled to a circuit operating at a high voltage (HV
DD
).
Such mixed voltage integrated circuitry typically includes an output buffer having an input coupled to an output of the circuit operating at LV
DD
, and having an output coupled via a bus to an input or output of the circuit operating at HV
DD
. An input buffer for the circuit operating at LV
DD
is also coupled to the bus in some instances.
Many conventional output buffers operate improperly or fail structurally when used in mixed voltage integrated circuitry. Signals at HV
DD
received at the output of a conventional output buffer can forward bias a drain/body semiconductor junction of a transistor or transistors in the output buffer. Further, a signal at HV
DD
on the bus can trigger a latch-up of these transistors. Such latch-up typically results in erroneously asserted signals at output and high leakage currents, and sometimes causes structural failure of the output buffer. Further, such latch-up can bum an IC Chip on which the output buffer is fabricated.
One type of conventional output buffer used in mixed voltage integrated circuitry includes a field effect transistor (FET) fabricated within a well that switches from receiving LV
DD
from an LV
DD
supply to receiving HV
DD
from a signal at HV
DD
on the bus. This type of well is commonly called a “floating well” because the voltage of the well can rise along with the voltage on the bus. A floating well typically is implemented in an output stage FET that drives the bus, as follows. The well and source of the output stage FET are coupled together using a first diode. The well and drain of the output stage FET are coupled together using a second diode. Finally, the well of the output stage FET is coupled to the source of a pre-output stage FET that drives the gate of the output stage FET.
A floating well is difficult to implement properly because the switching time for the floating well is highly dependent on layout pattern and operation of the diodes and transistors in the output and pre-output stages, and on the impedance of the bus and circuitry coupled to the bus. Further, the diodes used typically must have a low cut-in voltage for the floating well to operate properly. Fabrication of such diodes requires an expensive additional manufacturing procedure.
There is thus a continuing need for an improved output buffer for use in mixed voltage integrated circuitry. Such an output buffer should preferably be able to couple a circuit operating at LV
DD
to a circuit operating at HV
DD
, and preferably should not suffer the device failure and improper operation encountered in conventional output buffers. Further, such an output buffer should preferably be easy to manufacture, operate quickly and reliably, and be highly tolerant to signals at HV
DD
received from the bus or other circuitry.
SUMMARY OF THE INVENTION
The present invention overcomes the device failure and improper operation encountered in conventional output buffers with a voltage tolerant output buffer for use in mixed voltage integrated circuitry. The voltage tolerant output buffer couples a circuit operating at LV
DD
(LV
DD
circuit) to a circuit operating alternatively at HV
DD
or LV
DD
(HLV
DD
circuit), where LV
DD
is lower than HV
DD
. Unlike conventional output buffers, signals at HV
DD
from the HLV
DD
circuit will not induce latch-up or other improper operation of the voltage tolerant output buffer.
The voltage tolerant output buffer features a transistor having a body that is coupled to an HV
DD
supply. As used herein, the body of a transistor is defined to mean that region of semiconductor material which includes the conductive channel of the transistor when the transistor is turned ON. The HV
DD
supply maintains proper bias of a semiconductor junction defined between the body and an output of the transistor. The voltage tolerant output buffer also features asserting a high signal at HV
DD
to an input of this transistor to turn OFF the transistor fully, regardless of the voltage on the output.
One embodiment of the voltage tolerant output buffer comprises a driver and a voltage translator. The driver comprises a pull-up p-channel field effect transistor (PFET) and a pull-down n-channel field effect transistor (NFET). The source of the pull-up PFET is coupled to an LV
DD
supply. The source and body of the pull-down NFET are coupled to a ground voltage of V
SS
that is lower than LV
DD
. The drains of the pull-up PFET and pull-down NFET are coupled together to form an output of the voltage tolerant output buffer. The output of the voltage tolerant output buffer is coupled via a bus to an input and/or output of the HLV
DD
circuit.
The body of the pull-up PFET is coupled to an HV
DD
supply. The HV
DD
supply maintains reverse bias of a drain/body semiconductor junction in the pull-up PFET even while signals at HV
DD
are on the drain of this PFET. The reverse bias of the drain/body semiconductor junction substantially reduces leakage currents and eliminates latch-up in the voltage tolerant output buffer. Both the HV
DD
supply and the LV
DD
supply are preferably incorporated in the LV
DD
circuit, but can be incorporated in other circuitry.
The LV
DD
circuit, voltage translator, and driver are coupled together as follows. The LV
DD
circuit has first and second outputs. The first output is coupled to an input of the voltage translator. The second output is coupled to the gate of the pull-down NFET of the driver. The voltage translator has an output responsive to signals received at the input thereof. The output of the voltage translator is coupled to the gate of the pull-up PFET of the driver.
Signals from the second output of the LV
DD
circuit control the gate of the pull-down NFET in a conventional manner. Signals from the first output of the LV
DD
circuit control the gate of the pull-up PFET of the driver as follows. In response to receiving a low signal at V
SS
from the LV
DD
circuit, the voltage translator asserts a low signal at V
SS
to the gate of the pull-up PFET of the driver. This low signal at V
SS
turns ON the pull-up PFET to assert a high signal at LV
DD
on the bus. However, in response to receiving a high signal at LV
DD
from the LV
DD
circuit, the voltage translator asserts a high signal at HV
DD
to the gate of the pull-up PFET of the driver. The high signal at HV
DD
asserted by the voltage translator is thus at a higher voltage level than the high signal at LV
DD
that was received by the voltage translator from the LV
DD
circuit. The high signal at HV
DD
beneficially turns OFF the pull-up PFET regardless of the voltage on the drain of the pull-up PFET.
More particularly, to ensure that a PFET is turned OFF, the gate of the PFET must be at a voltage at least as high as the higher of the voltage on the source and the voltage on the drain. In the driver, the voltage on the source of the pull-up PFET is at LV
DD
. However, the drain of the pull-up PFET can be a voltage level above LV
DD
. In particular, a high signal at HV
DD
on the bus typically raises the voltage on the drain of the pull-up PFET higher than the LV
DD
voltage on

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