Voltage supply isolation buffer

Details Voltage supply isolation buffer Voltage supply isolation buffer

1994-08-30

1996-08-06

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 81, 326 68, 326 33, 326 34, 327328, 327543, 327546, H03K 190175, H03K 19094

Patent

active

055437346

ABSTRACT:
A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

REFERENCES:
patent: 4122360 (1978-10-01), Kawagai et al.
patent: 4937477 (1990-06-01), Tsoi et al.
patent: 5117131 (1992-05-01), Ochi et al.
patent: 5202591 (1993-04-01), Walden
patent: 5208488 (1993-05-01), Takiba et al.
patent: 5331224 (1994-07-01), Ohannes et al.

Affiliated with

Also associated with

Rating

Voltage supply isolation buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage supply isolation buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage supply isolation buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2193539