Voltage stress test circuit for a DRAM

Details Voltage stress test circuit for a DRAM Voltage stress test circuit for a DRAM

1993-06-11

1995-01-10

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365193, 365222, 365236, G11C 700

Patent

active

053813731

ABSTRACT:
A semiconductor memory device includes a circuit for generating a voltage stress mode signal on the basis of a predetermined signal used in a normal operation of a DRAM circuit, and a control circuit for receiving the test mode signal from the generating circuit and performing control such that, in an AC voltage stress test mode, upper bits, of an output signal from a refresh address counter, which are more significant than a specific bit are fixed at the same level, and lower bits less significant than the specific bit are subjected to a normal count operation and such that, in a DC voltage stress test mode, all the bits of an output signal from the refresh address counter are fixed at the same level so as to cause a word line driving circuit to simultaneously drive all the word lines. In setting a desired AC/DC voltage stress mode for a DRAM in a wafer state or a package state, no special voltage stress test pads are required, and the number of circuits other than the circuit required for the normal mode can be minimized, thereby reducing an increase in chip area. In addition, in the AC mode, any failure mode such as a decrease in breakdown voltage between adjacent word lines or adjacent bit lines can be simultaneously screened.

REFERENCES:
patent: 5249155 (1993-09-01), Arimoto et al.
patent: 5258954 (1993-11-01), Furuyama

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