Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-06-26
2001-09-04
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185230
Reexamination Certificate
active
06285614
ABSTRACT:
TECHNICAL FIELD
This invention relates to a voltage regulator for memory circuit. The invention also refers to a program structure for the drain voltage of a single feed memory cell, of the type comprising at least one voltage regulator with an output terminal connected to a drain terminal of the memory cell by means of a series comprising a program selection block and a column decoder.
More in particular, but not limiting itself thereto, the invention concerns a voltage regulator for single voltage Flash memory cells and the following specification is specifically orientated towards this field of application with the sole scope of simplifying its presentation.
BACKGROUND OF THE INVENTION
As is well known, electrically programmable non-volatile memories are is structured in cell matrix each of which comprises an MOS transistor with floating gate and relative areas of drain and source.
The programming of a memory cell is strongly influenced by a vd voltage applied to its drain terminal. In particular, for the non-volatile FLASH type memory cells, a reduced degree of vd drain voltage means a slow and insufficient programming of the cell, whilst an excessive degree of voltage leads to a partial erasing of the cell (so-called ‘soft-erasing phenomenon’).
The preceding considerations bring us to the conclusion that it is necessary to provide the circuit comprising the Flash memory with a voltage regulator which is particularly refined and precise in providing the correct drain voltage to the cells to be programmed.
A first technical solution known to satisfy this requirement consists of the so-called differential adjustment, illustrated in
FIG. 1
for an M
1
non-volatile single feed voltage memory cell.
In particular, the memory cell M
1
is inserted between a ground voltage reference GND and a programming voltage reference Vpd. This programming voltage reference Vpd is suitably derived from a boosted voltage Vpump obtained by means of a booster circuit
1
, for example of the load pump type.
The drain terminal D
1
of the memory cell M
1
is connected to the programming voltage reference Vpd via the series of a program selection block, or program load
2
, and a column decoder
3
. The program load block
2
consists conventionally of a logical inverter IL
1
and a transistor M
2
, in particular of the PMOS type. In practice, the program load block
2
represents a family of ‘on’ switches for the column decoder
3
.
The column decoder
3
consists of a chain of decoding transistors, having control terminals Y
0
, YN, YM which are connected to a first reference voltage for the decoding of the Vpcy column.
The drain voltage Vd of the memory cell M
1
is therefore given by the difference between the programming voltage Vpd and a &Dgr;V
c
equal to a drop in voltage due to the chain of decoding transistors Y
0
, YN, YM, of the decoder
3
, as well as serial resistors of the ‘bit line’, r
d
, and of the source terminal, r
s
:
Vd=Vpd−&Dgr;V
c
(1)
In order to limit such a drop in &Dgr;V
c
voltage the Vpcy column decoder voltage to be applied to the terminal decoding ports of the transistor chain Y
0
, YN, YM of the decoder
3
must be raised, in order to keep them in the so-called ‘triode’ operating zone.
The control terminal G
1
of the memory cell M
1
is in the same view connected to the second Vpcx row decoder voltage reference.
The programming voltage reference Vpd is on an output terminal OUT of a differential regulator
4
.
Such differential regulator
4
, comprising a differential stage
5
controlled by the boosted voltage Vpump generated by the booster circuit
1
, is for limiting the current which flows in the M
1
memory cell during the programming phase by stabilizing programming voltage Vpd.
Such differential stage
5
has an inverting input terminal
7
, connected to a bandgap circuit
6
, a non-inverting input terminal
8
, connected to a ground reference GND by means of an initial R
1
resistive element, and an output terminal
9
, connected to the output terminal OUT of the differential regulator
4
, as well as a feedback connection to a feed terminal
10
by means of a connecting transistor M
3
.
Such feed terminal
10
of the differential stage
5
is also connected to a booster circuit
1
which supplies the boosted voltage Vpump.
Furthermore, the output terminal OUT of the differential regulator
4
is connected to the ground reference GND by means of a filtering and compensation capacitance Cf as well as to the non-inverting input terminal
8
of the differential stage
5
, by means of a second resistive element R
2
.
Thanks to the above mentioned differential regulator
4
, the programming voltage Vpd for the drain terminal D
1
of the memory cell M
1
is obtained from a voltage control V
BG
supplied by a bandgap circuit
6
at the inverting input terminal
7
of the differential stage
5
.
In particular, the connecting transistor M
3
is a PMOS type pass transistor, controlled by the differential stage
5
, in order to produce a voltage transfer between the boosted voltage Vpump and the programming voltage Vpd. Such pass transistor M
3
puts the load pump booster in communication with the bit-line comprising the memory cell M
1
, therefore making full use of the boosted voltage Vpump.
In fact, when its control terminal receives the boosted voltage Vpump, the connecting transistor M
3
is off and takes the programming voltage Vpd present on the output terminal OUT of the differential regulator
4
to ground GND. In parallel, when the control terminal thereof is subjected to a ground voltage GND, the connecting transistor M
3
is operating in the ohmic zone and transfers the entire boosted voltage Vpump onto the output terminal OUT of the differential regulator
4
.
In other words, the connecting transistor M
3
switches the booster circuit
1
connection on and off at the charge pump with the bit-line of the memory cell M
1
.
Finally, the presence of the filtering and compensation capacitance Cf, in correspondence to the output terminal OUT of the differential regulator
4
, carries out a compensation of the structure in its whole, allowing at the same time for a load storage which is useful in the first stages of the programming of the cell M
1
.
Such filtering and compensation capacitance Cf is conveniently of the value of some tens of picofarads. In mathematical terms, it introduces a pole in the transfer function of the differential regulator
4
.
It is useful to note that the filtering and compensation capacitance Cf could not be substituted, for the scope of compensation, via a Miller capacitance placed between terminals
9
and OUT, since the difference of potential between these terminals can undergo inversions according to the conditions of the operating of the device.
The differential regulator
4
also has drawbacks, of which the most important is in that it makes use of a PMOS transistor as a connecting transistor M
3
.
In fact this PMOS transistor must be configured at a common source terminal (common source configuration), in this way making the loop gain of the structure comprising the differential regulator
4
, the program load
2
and the column decoder
3
dependent on the number of cells programmed and increase accordingly, in consequence, the value of this gain.
More precisely, the loop gain of the structure is therefore given in the following formula:
G
LOOP
=A
0
(S)*g
(PMOS)
*R1/(1+SCf(R1+R2)) (2)
wherein: A
0
(S) is the gain of the differential stage
5
;
g
m (PMOS)
is the transconductance of the PMOS type connecting transistor M
3
.
The loop gain G
LOOP
of the structure, represented by the above mentioned formula (2) depends disadvantageously on the number of programmed cells controlled by the differential stage
5
. In fact, the g
m(PMOS)
transconductance of the connecting transistor M
3
increases as the current absorbed at the output terminal OUT of the differential regulator
4
increases, this current depending on the number of cells programmed (i.e., the number of cells whe
Branchetti Maurizio
Carrera Marcello
Mulatti Jacopo
Zanardi Stefano
Elms Richard
Galanthay Theodore E.
Iannucci Robert
Phung Anh
Seed IP Law Group PLLC
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