Voltage referencing clock for source-synchronous multi-level...

Details Voltage referencing clock for source-synchronous multi-level... Voltage referencing clock for source-synchronous multi-level...

2007-01-23

2010-10-26

Tran, Vincent T (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C326S093000, C326S105000

Reexamination Certificate

active

07823003

ABSTRACT:
An input circuit is provided for coupling to a source-synchronous multi-level bus carrying data, clock, and complementary clock signals. The clock and complementary clock signals have a less than full voltage swing than the data signal so they can act as reference voltages for the data signal. The circuit includes a first differential receiver having inputs coupled to the data and the clock signals, a second differential receiver having inputs coupled to the data signal and a reference signal, and a third differential receiver having inputs coupled to the data and the complementary clock signals. The circuit further includes first, second, and third flip-flops having data inputs coupled to outputs of the first, the second, and the third differential receivers, and clock inputs coupled to a delayed clock signal generated from the clock and the complementary clock signals. The outputs of the flip-flops determine the level of the data signal.

REFERENCES:
patent: 6317469 (2001-11-01), Herbert
patent: 6477205 (2002-11-01), Doblar et al.
patent: 6762623 (2004-07-01), Suryanarayana et al.
patent: 2007/0046334 (2007-03-01), Hairapetian
patent: 2008/0211543 (2008-09-01), Gruijl

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