Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2003-05-15
2004-06-08
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189090, C365S185180
Reexamination Certificate
active
06747905
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a voltage recovery switch, and more specifically, to a voltage recovery switch without device breakdown issue in non-volatile memory.
2. Description of the Prior Art
Memory is one of the most important components in electronic products and is categorized into two types: volatile memory and non-volatile memory. Since data stored in non-volatile memory can remain in the memory cells even the power supply connected to the non-volatile memory is shut down, non-volatile memory, such as flash memory, is more frequently used in various electronic products than volatile memory is.
According to the prior art, a non-volatile memory cell is formed on a substrate and comprises a source, a drain, and a stacked gate. Normally, the stacked gate comprises floating gate and a control gate, and a silicon oxide layer is positioned between either the floating gate and the substrate or the control gate and the floating gate to isolate either two of the substrate, the floating gate, and the control gate. The stacked gate technique used in non-volatile memory applies a high potential voltage to the control gate to change stored electron amounts in the floating gate by either electron FN tunneling effects or hot electron injection, which eventually changes the threshold voltage of the select gate and records data.
Generally, the non-volatile memory comprises a charge pump for generating the high potential voltages previously mentioned, such as a positive voltage of 10V and a negative voltage of 10V, for the purpose of programming or erasing of the non-volatile memory. After programming or erasing of the non-volatile memory, the non-volatile memory works at a power supply voltage level, normally between an operating voltage V
dd
of +3V and a grounded voltage of 0V. Simultaneously, the charge pump is turned off, and the high potential voltages are discharged by the power supply voltage. However, a bounce phenomenon of the voltage level of the power supply voltage frequently occurs when the huge amount of charges are directly conducted from the high potential voltages to the power supply voltage, such as electrically connecting a positive voltage of +10V and a negative voltage of 10V respectively to the operating voltage V
dd
and the grounded voltage, leading to noise and malfunction of the voltage recovery switch.
In order to prevent the bounce phenomenon previously mentioned, a voltage recovery switch is frequently employed in the non-volatile memory according to the prior art to electrically connect the high potential voltages to neutralize positive and negative charges in the high potential voltages until the high potential voltages are mildly decreased to a lower voltage level. The high potential voltages are then electrically connected to the power supply voltage for further discharge. Since most portions of the positive and negative charges in the high potential voltages are neutralized by the voltage recovery switch,the bounce phenomenon during the discharge of the high potential voltages by the power supply voltage is limited to be within an acceptable range.
Please refer to
FIG. 1
showing a schematic view of a voltage recovery switch
10
according to the prior art. As shown in
FIG. 1
, the voltage recovery switch
10
comprises a first NMOS transistor
12
, a PMOS transistor
14
, and a second NMOS transistor
16
. A drain and a gate of the first NMOS transistor
12
are electrically connected to the positive voltage of +10V and a first control signal CTRL
1
, respectively, and a source and a gate of the PMOS transistor
14
are electrically connected to a source of the first NMOS transistor
12
and a voltage with a constant voltage level, such as the grounded voltage, respectively. A drain, a gate, and a source of the second NMOS transistor
16
are electrically connected to a drain of the PMOS transistor
14
, a second control signal CTRL
2
, and the negative voltage of 10V, respectively. The structure of the voltage recovery switch
10
is revealed in JSSC 2000 November, “A Channel-Erasing 1.8V-Only 32 Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme” and is abbreviated for simplicity of description.
The first and second control signals CTRL
1
and CTRL
2
are employed to respectively turn off the first and second NMOS transistors
12
and
16
during programming or erasing of the voltage recovery switch
10
to prevent neutralizing discharge of the positive and negative voltages. After the programming or erasing of the non-volatile memory, the first and second control signals CTRL
1
and CTRL
2
are employed to respectively turn on the first and second NMOS transistors
12
and
16
, so as to neutralize and therefore discharge the positive and negative voltages by the voltage recovery switch
10
.
The first NMOS transistor
12
can be directly control by a logical signal, such as the first control signal CTRL switching between 3V and 0V. However, The second NMOS transistor
16
is electrically connected to a negative voltage having a large absolute value, such as a voltage of 10V, and can only be operated in a cut-off region when a negative voltage V
N
is applied on the second NMOS transistor
16
by the second control signal CTRL
2
. In order to control the second NMOS transistor
16
, the second control signal CTRL
2
needs to be a control signal switching between the negative voltage V
N
and 0V. As a result, the cost for the circuit design of the non-volatile memory is much increased. In addition, as the second NMOS transistor
16
is turned on, the voltage difference between the gate and the source of the second NMOS transistor
16
is 13V, which frequently leads to breakdown of the second NMOS transistor
16
.
SUMMARY OF INVENTION
It is therefore a primary object of the present invention to provide a voltage recovery switch so as to prevent device breakdown of transistors in a non-volatile memory.
According to the claimed invention, the voltage recovery switch is employed for neutralizing a first voltage and a second voltage in a non-volatile memory. The voltage recovery switch comprises a first PMOS transistor, an NMOS transistor, and a second PMOS transistor. A gate of the first PMOS transistor is electrically connected to a third voltage, and a source of the first PMOS transistor is electrically connected to the first voltage. A gate of the NMOS transistor is electrically connected to a control signal, and a drain of the NMOS transistor is electrically connected to a drain of the first PMOS transistor. A gate of the second PMOS transistor is electrically connected to a fourth voltage, a source of the second PMOS transistor is electrically connected to a source of the NMOS transistor, and a drain of the second PMOS transistor Is electrically connected to the second voltage.
It is an advantage of the present invention over the prior art that the control signal of the voltage recovery switch employed to control the NMOS transistor is a frequently adapted logical signal. The cost burden for the circuit design of the non-volatile memory as revealed in the prior art is therefore prevented. In addition, the second PMOS transistor is inserted between the NMOS transistor and the second voltage. The voltage difference between the gate and the source of the NMOS transistor is well controlled, preventing breakdown of the NMOS transistor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.
REFERENCES:
patent: 4694430 (1987-09-01), Rosier
patent: 4835423 (1989-05-01), de Ferron et al.
patent: 4875188 (1989-10-01), Jungroth
patent: 6366505 (2002-04-01), Fournel
patent: 6477091 (2002-11-01), Tedrow et al.
e-Memory Technology, Inc.
Hsu Winston
Phung Anh
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