Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-05-09
2004-06-01
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000, C326S030000, C327S321000, C327S513000, C327S378000, C327S108000, C327S087000
Reexamination Certificate
active
06744280
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to electrical circuits and more particularly to current driven differential drivers.
BACKGROUND OF INVENTION
In a typical communication system, inter-chip high-speed communication is generally limited by the performance of driver and receiver circuits at the interface of communicating chips. Standards have been established for high-speed signal handling applications including, for example, low voltage differential signaling (LVDS) and positive emitter-coupled logic (PECL). These standards enable the design of high-speed systems with minimum power dissipation and low electromagnetic interference (EMI). However, inter-chip high-speed communication is still limited by the performance of driver and receiver circuits at the interface of these devices. The LVDS TIA/EIA-644 standard specifies an output voltage through 100 Ohms to be within 247 mv to 454 mv. This provides sufficient signal amplitude for transforming data without overdriving the connected receiver.
One limitation involves a condition known as low voltage output differential (VOD). The VOD of a differential driver is the voltage differential between the two components of the differential output signal. In systems employing LVDS, the VOD is designed to be on the order of about 400 mv. In LVDS, the lower voltage output of the differential pair is typically 1.0 V while the higher output voltage is typically 1.4 V. The difference between the two is about 400 mv while the average of the two is the common mode voltage, V
CM
. For the above example, V
CM
is about 1.2V. The VOD is created by steering a constant current from one output terminal though a standard 100 ohm load resistor to the other output terminal. Current generators are typically used to establish the output currents, I
SOURCE
and I
SINK
at the two respective output terminals. When process variations cause output current sources to provide I
SOURCE
and I
SINK
values that are below specified levels, then the resulting VOD will be low. A low VOD reduces the noise immunity within the LVDS system and can impact total system performance. Low output currents often result from process variations in resistors that are used to determine the current values. As process limitations can produce variations of plus or minus 20% in resistor values, the corresponding output currents are also subject to plus or minus 20% variations that result in similar variations of VOD.
SUMMARY OF INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to system and methods for compensating the Voltage Output Differential (VOD) of current driven driver circuits (e.g., LVDS driver circuits) to maintain a desired VOD during driver operation. The system and methods provide for monitoring internal circuit performance and correcting for variations in output current supplied to maintain a desired VOD between the two differential output signals. The present invention provides for comparing the voltage of a representative signal that is based on the VOD with a reference signal that is set to a desired voltage level based on a desired VOD. By determining whether the representative voltage level is higher, equal to, or lower than the desired reference level, balanced adjustments may be made to at least one of the output current source level and the output current sink level to alter the VOD. Balancing the adjustment to the two current sources maintains the existing desired common mode voltage (V
CM
). A balanced increase in the source and sink currents at the output results in an increased, VOD while a balanced decrease in the source and sink currents results in a decrease in VOD.
In one aspect of the present invention, a representative DC signal of the VOD is compared with a reference signal that is set to a desired level. The representative DC signal varies in voltage level by a known offset. The reference signal is set to a value equal to the desired output voltage level plus the known offset. A common mode voltage (V
CM
) regulator is employed to maintain V
CM
equal to the average of the two output voltage levels. Since V
CM
is known, monitoring either the higher differential output voltage or the lower differential output voltage is equivalent to monitoring the VOD. If VOD is low, the output source current and/or the output sink current is increased such that VOD is restored to the desired level. This is accomplished by increasing (e.g., adding) current to a current source that is reflected to at least one of the source current and sink current until the desired VOD is achieved. Similarly, if VOD is high, one or both of the output source current and output sink current are decreased such that VOD is restored to the desired level. This is accomplished by decreasing the current to a current source that is reflected to one or both the source current and the sink current until the desired VOD is achieved.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
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patent: 6208161 (2001-03-01), Suda
patent: 6246262 (2001-06-01), Morgan et al.
patent: 6285232 (2001-09-01), Hasegawa
patent: 6288581 (2001-09-01), Wong
patent: 6297685 (2001-10-01), Ewen et al.
patent: 6313662 (2001-11-01), Ide
patent: 6369621 (2002-04-01), Tinsley et al.
patent: 6411146 (2002-06-01), Kuo
Carvajal Fernando D.
Morgan Mark W.
Brady W. James
Swayze, Jr. W. Daniel
Tan Vibol
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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