Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-09-13
2003-03-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000
Reexamination Certificate
active
06529037
ABSTRACT:
FIELD
The present invention relates generally to digital data ports, and more specifically to bidirectional digital data ports.
BACKGROUND OF THE INVENTION
Integrated circuits typically communicate with other integrated circuits on wires that are part of a “bus.” A typical bus includes many wires, or circuit board traces, connecting multiple integrated circuits. Some buses are “unidirectional,” because signals only travel in one direction on each wire of the bus. Other buses are “bidirectional,” because signals travel in more than one direction on each wire of the bus. In the past, most bidirectional buses were not “simultaneously bidirectional,” because multiple signals did not travel on the same wire in opposite directions at the same time; instead, the bus was shared over time, and different signals traveled in different directions at different points in time. Some newer buses are “simultaneous bidirectional” buses. Simultaneous bidirectional buses allow data to travel in two directions on a single wire at the same time.
Before reliable communications can take place on a bus, the integrated circuits need to be ready to communicate, or be “synchronized,” and each circuit on the bus should have information regarding the readiness of other circuits on the bus. Some circuits may need to be initialized, while others may need to become stabilized. In some bus applications, it can take an indeterminate amount of time for circuits to become ready to reliably communicate. It can be important to not drive data onto a bus until the intended receiver is ready to receive the data, especially in simultaneous bidirectional bus applications, where data is being driven in both directions at once.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and apparatus to provide a synchronization mechanism for simultaneous bidirectional data buses.
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Haycock Matthew B.
Martin Aaron K.
Mooney Stephen R.
Cho James H.
Schwegman Lundberg Woessner & Kluth P.A.
Tokar Michael
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