Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-04-27
2002-05-07
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000
Reexamination Certificate
active
06384631
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to integrated circuits and, in particular, to voltage level shifters for driving output lines of an integrated circuit.
BACKGROUND OF THE INVENTION
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the overall system.
Reductions in power consumption are particularly important in SOC devices. SOC devices are frequently used in portable devices that operate on battery power. Since maximizing battery life is a critical design objective in a portable device, it is essential to minimize the power consumption of SOC devices that may be used in the portable device. Furthermore, even if an SOC device is not used in a portable device, minimizing power consumption is still an important objective. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in the United States, particularly California.
To minimize power consumption in electronic devices, particularly SOC devices, many manufacturers have reduced the voltage levels at which electronic components operate. Low power is integrated circuit (IC) technology operating at +3.3 volts replaced IC technology operating at +5.0 volts. The +3.3 volt IC technology was, in turn, replaced by +1.6 volt IC technology in many applications, particularly microprocessor and memory applications.
However, as the operating voltage of an integrated circuit is reduced, the noise margins of the integrated circuit are also reduced. Thus, an integrated circuit operating at +1.5 volts has smaller noise margins than a circuit operating at +3.3 volts. In deep submicron VLSI designs, two voltage sources for a chip design are common. One voltage source is an internal core power supply voltage (i.e., VDD) that has a lower swing voltage than the second voltage source, which provides the output pad ring voltage (i.e., VDDI/O). Common range values may include a VDD of 1-1.5 volts and a VDDI/O range of 2.3-3.6 volts.
The internal core circuitry running on VDD typically uses thin gate oxides and cannot tolerate the higher external voltages of 2.3-3.6 volts. The transistors used in the pad rings, which interface off the chip to the board and surrounding chips, use a thicker gate oxide and larger minimum L than internal transistors and hence can handle the larger external voltages.
In order for the low voltage transistors to communicate across the boundary from the 1 volt domain to the higher 2.5 volt (typical voltage), some type of voltage level translation must occur. When chip technologies still used internal voltages greater than 2 volts and external voltages were 3.3-5.5 volts, this level translation was relatively easy, and several different methodologies could be used. However, once internal voltages decreased to the 1 volt range, several of the previously used level translation methodologies could no longer be used.
Many processing systems implement conditions in which the output power supply, VDDI/O, may be powered up while the internal core power supply, VDD, is zero. Under this condition, it is desirable to disable the line drivers for the output pads. There are numerous methods for forcing output lines into a high-impendance tristate condition when VDDI/O is powered up and VDD is not. However, most of these methods require a trickle current to establish Vbe values and VDS. A method for accomplishing this without current draw is desirable, especially for systems which run on batteries and may need to go into low-power modes. If this tri-stating function could be accomplished without adding more circuitry, that would be an even larger bonus. Therefore, there is a need in the art for integrated circuits in which output line drivers may be powered up to a known state while internal core circuitry is not powered up. More particularly, there is a need for improved integrated circuits in which output line drivers may be powered up to a high impedance tri-state condition without requiring additional power-on biasing circuitry or extensive design of existing devices.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a voltage level shifter capable of receiving an input signal having a maximum Logic 1 value of VDD and producing an output signal having a maximum Logic 1 value of VVDI/O, where VDDI/O is greater than VDD. According to an advantageous embodiment of the present invention, the voltage level shifter comprises: 1) a first circuit branch comprising A) a first p-type transistor having a source coupled to a first power supply having a level of VDDI/O and B) a first n-type transistor having a source coupled to ground, a drain coupled to a drain of the first p-type transistor, and a gate coupled to the input data signal; and 2) a second circuit branch comprising A) a second p-type transistor having a source coupled to the first power supply and a gate coupled to a drain of the first n-type transistor and B) a second n-type transistor having a source coupled to ground, a drain coupled to i) a drain of the second p-type transistor and ii) a gate of the first p-type transistor, and a gate coupled to an inverted copy of the input data signal, wherein a drain current of the first p-type transistor is larger than a drain current of the second p-type transistor for the same gate-to-source voltage, such that the first p-type transistor turns on faster than the second p-type transistor if the first power supply is powered up to VDDI/O when the first and second n-type transistors are off.
According to one embodiment of the present invention, a size of the first p-type transistor is larger than a size of the second p-type transistor.
According to another embodiment of the present invention, the first and second n-type transistors are identical.
According to still another embodiment of the present invention, the voltage level shifter further comprises a first inverter having an input coupled to the input data signal and an output coupled to the gate of the second n-type transistor.
According to yet another embodiment of the present invention, the voltage level shifter further comprising a second inverter having an input coupled to the gate of the second p-type transistor.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives ther
Ballachino William E.
Wert Joseph D.
Le Don Phu
National Semiconductor Corporation
Tokar Michael
LandOfFree
Voltage level shifter with high impedance tri-state output... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Voltage level shifter with high impedance tri-state output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage level shifter with high impedance tri-state output... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2838303