Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2001-06-08
2002-09-03
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189110, C365S185230, C326S080000, C326S082000
Reexamination Certificate
active
06445622
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a voltage level shifter circuit for shifting a voltage of an input signal to a higher voltage and a nonvolatile semiconductor storage device using the circuit.
Conventionally, there has been ETOX (EPROM THIN OXIDE: Trademark of Intel Corporation) as a flash memory (whole erase type memory) used most generally.
FIG. 5
shows a schematic sectional view of the flash memory cell of this ETOX type. In
FIG. 5
, a floating gate
5
is formed on a substrate (well)
3
between a source
1
and a drain
2
via a tunnel oxide film
4
. Furthermore, a control gate
7
is formed on the floating gate
5
via a layer insulation film
6
.
The operational principle of the ETOX type flash memory will be described next. Table 1 shows an example of application voltages in the modes of write, erase and read.
As shown in Table 1 , a voltage Vpp of 10 V is applied to the control gate
7
in the case of write, a reference voltage Vss of 0 V is applied to the source
1
, and a voltage Vpgd of 6 V is applied to the drain
2
. By the above operation, a large current (500 &mgr;A per cell) flows through a channel layer. In the above stage, channel hot electrons are generated in a channel portion of a high electric field on the side of the drain
2
. As a consequence, the electrons are injected from the channel portion into the floating gate
5
, causing an increase in a threshold voltage. Thus, there is executed write into the memory cell in which write should be done. In the column of the drain
2
in Table 1, 0 V written side by side with 6 V is an application voltage to the drain
2
of the memory cell that is not subjected to write.
TABLE 1
Control
Gate 7
Drain 2
Source 1
Substrate 3
Write
10 V
6 V/0 V
0 V
0 V
Erase
−9 V
Open
6 V
0 V
Read
3 V
1 V
1 V
0 V
In the case of erase, a voltage Vnn of −9 V is applied to the control gate
7
, a voltage Vpe of 6 V is applied to the source
1
, and the drain
2
is made open. The erase of the memory cell is thus executed with the threshold voltage reduced by extracting electrons to the source
1
.
In the case of read of the memory cell that has been written (programmed) or erased as described above, there are applied a voltage of 3 V to the control gate
7
, a voltage of 1 V to the drain
2
and a voltage of 0 V to the source
1
. When data stored in the memory cell is in a written state, no cell current flows and thus it is judged that the stored data is “0”. This is because the threshold voltage of the memory cell is not lower than 3.5 V. When data of the memory cell is in an erased state, the threshold voltage is not higher than 2.0 V, and therefore a cell current flows and it is judged that the stored data is “1”. It is to be noted that the above-mentioned judgment is executed by sensing a current that flows from the drain
2
to the source
1
by means of a sense circuit (not shown) provided on the side of the drain
2
.
For devices that use a voltage different from a voltage of an input signal during write, erase and read, there is EPROM (Erasable and Programmable Read Only Memory) such as an ultraviolet erasable type EPROM besides the above-stated flash memory. In these devices, the voltage applied to each node is varied during write, erase and read, as described above. Moreover, a voltage higher than Vcc (power voltage) is necessary during write and read. Therefore, the voltage of the input signal is required to be shifted to a higher voltage in the device. A circuit used in this case is called a level shifter circuit. The aforementioned power voltage Vcc takes the value of 1.8 V, 3 V or 5 V for example. In contrast to this, the value of 8 V, 10 V or 12 V is taken as a high voltage.
Conventionally, as the aforementioned level shifter circuit, there has been a high voltage level shifter circuit as disclosed in Japanese Patent Laid-Open Publication No. HEI 6-236694. Operation of the high voltage level shifter circuit will be described below with reference to FIG.
6
. In
FIG. 6
, the voltage of Vpp e.g. 12 V is applied as a voltage hvpp. In this state, when a power voltage Vcc e.g. 1.8 V is inputted as an input signal “in”, then a transistor Tr
3
is turned on and a transistor Tr
4
, to which the input signal “in” is inputted via an inverter INV
1
, is turned off. By the above operation, a transistor Tr
2
is turned on, and a transistor Tr
1
is turned off. As a result, a voltage at a level of Vpp e.g. 12 V is outputted as an output signal “out”.
On the other hand, when the reference voltage Vss e.g. 0 V is applied as the input signal “in”, the transistor Tr
3
is turned off, while the transistor Tr
4
is turned on. By the above operation, the transistor Tr
2
is turned off, and the transistor Tr
1
is turned on. As a result, a voltage at a level of Vpp e.g. 12 V is outputted as an output signal “outb”, and a voltage at Vss level is outputted as the output signal “out”.
Therefore, in the aforementioned high voltage level shifter circuit, the level of the input signal “in” is shifted from (Vcc−Vss) to (Vpp−Vss). In this case, the output signal “outb” is a signal obtained by inverting the level of the output signal “out”.
However, the high voltage level shifter circuit shown in
FIG. 6
has the following problems. That is, considered is the case where the level of the input signal makes the transition from “H” to “L” in a state in which the voltage hvpp is Vpp e.g. 12 V and the level of the output signal “out” is “H” (i.e., Vpp e.g. 12 V). In this case, the drain voltage of an n-MOS (Metal-Oxide Semiconductor) transistor Tr
4
prior to the transition of the level of the input signal “in” is Vpp, while a gate voltage and a source voltage are each Vss e.g. 0 V. If the level of the input signal “in” makes a transition, then the gate of the n-MOS transistor Tr
4
changes from 0 V to 1.8 V. Consequently, there momentarily exists a state in which the transistor Tr
4
is turned on and the gate voltage is lower than the drain voltage. This corresponds to, for example, a state in which the drain voltage is between 1.8 V and 12 V and the gate voltage is 1.8 V. In the above-mentioned state, a large amount of hot carriers are generated in a channel region between the source and the drain, and hot holes move toward the gate, consequently trapping the holes in the gate insulator of the transistor Tr
4
. If the above-mentioned operation is repeated, then the leak characteristic of the transistor Tr
4
in the OFF state is deteriorated. In this case, the n-MOS transistor Tr
3
, which is operating in a similar manner, is similarly deteriorated.
In the case of the flash memory, since the above-described write and erase operations are executed, the state in which holes are trapped in the gate insulator of the transistors will be repeated tens of thousands of times. Consequently, increased OFF-leak occurs in the high voltage level shifter circuit as shown in
FIG. 6
, and this incurs a current increase in a standby state in which the device is not operating.
Accordingly, it is considered to insert a cascade transistor for voltage alleviation use as disclosed in Japanese Patent Laid-Open Publication No. HEI 6-236694 as a means for solving the aforementioned problem.
FIG. 7
shows a circuit diagram of the high voltage level shifter circuit of the above type. As is apparent from
FIG. 7
, a cascade n-MOS transistor Tr
9
is interposed between a transistor Tr
5
and a transistor Tr
7
, while a cascade n-MOS transistor Tr
10
is interposed between a transistor Tr
6
and a transistor Tr
8
. A power voltage Vcc e.g. 1.8 V is applied to the gates of the cascade transistor Tr
9
and the cascade transistor Tr
10
. The operation of the high voltage level shifter circuit having the aforementioned circuit construction will be described below.
Before the level of the input signal “in” is transited from “H” to “L”, a voltage of 12 V is applied to a drain of the cascade transistor Tr
10
, a voltage of 1.8 V is applied to a gate of Tr
10
, and a source voltage of T
Morrison & Foerster / LLP
Nguyen Tan T.
Sharp Kabushiki Kaisha
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