Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
1998-02-19
2002-08-13
Lee, Michael G. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S080000, C326S081000, C326S086000, C326S121000
Reexamination Certificate
active
06433582
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage level shifter circuit for shifting a voltage of an input signal to a high voltage or a negative voltage.
2. Description of the Related Art
Devices using a voltage different from a voltage of an input signal include a flash memory and an electrically erasable and programmable read only memory (EEPROM). In such devices, a voltage of an input signal must be shifted to a high voltage or a negative voltage. A circuit for conducting such shifting is referred to as a level shifter. Note that, in this specification, a high voltage refers to a voltage higher than that of an input signal. A voltage of an input signal is 3 V or 5 V, for example. A high voltage is 8 V, 10 V or 12 V, for example.
Japanese Laid-Open Publication No. 6-236694 discloses a high voltage level shifting circuit as shown in FIG.
14
.
When a voltage at an input terminal T
1
is Vcc, a transistor N
1
is turned on, and a transistor N
2
is turned off. In this case, transistors P
2
and N
1
are turned on. As a result, the voltage level shifter circuit outputs from its output terminal T
2
a signal having a voltage Vpp through the transistor P
2
as well as outputs from its output terminal T
3
a signal having a voltage Vss through the transistor N
1
.
When a voltage at the input terminal T
1
is Vss, the transistors N
1
and P
2
are turned off, whereas the transistors N
2
and P
1
are turned on. As a result, the voltage level shifter circuit outputs from the output terminal T
2
a signal having a reference voltage Vss through the transistor N
2
as well as outputs from the output terminal T
3
a signal having a voltage Vpp through the transistor P
1
.
In this case, a voltage Vcc is 3 V, for example, a voltage Vss is 0 V, for example, and a high voltage Vpp is 10 V, for example.
Japanese Laid-Open Publication No. 58-125298 discloses a digital level shifter with low power consumption as shown in FIG.
15
.
When a voltage at an input terminal T
1
is Vcc, a voltage at a node nd
5
is Vss, whereby a transistor P
2
is turned on. In this case, a voltage at a node nd
6
is Vcc, whereby a transistor P
1
is turned off. As a result, the level shifter outputs a signal having a voltage Vpp from its output terminal T
2
as well as outputs a signal having a voltage Vss from its output terminal T
3
.
When a voltage at the input terminal T
1
is at Vss, a voltage at the node nd
5
is Vcc, whereby the transistor P
2
is turned off. In this case, a voltage at the node nd
6
is Vss, whereby the transistor P
1
is turned on. As a result, the level shifter outputs a signal having a voltage Vss from the output terminal T
2
as well as outputs a signal having a voltage Vpp from the output terminal T
3
.
FIG. 16
shows a general negative-voltage shifter circuit.
When a voltage at an input terminal T
1
is Vcc, a transistor P
1
is turned off, whereas a transistor P
2
is turned on. Therefore, a transistor N
1
is turned on, and a transistor N
2
is turned off. As a result, the negative-voltage shifter circuit outputs a signal having a voltage Vcc from its output terminal T
2
as well as outputs a signal having a voltage Vn from its output terminal T
3
.
When a voltage at the input terminal T
1
is Vss, the transistor P
1
is turned on, and the transistor P
2
is turned off. Therefore, the transistor N
1
is turned off, and the transistor N
2
is turned on. As a result, the negative-voltage shifter circuit outputs a signal having a voltage Vn from the output terminal T
2
as well as outputs a signal having a voltage Vcc from the output terminal T
3
.
In this case, a voltage Vcc is 3 V, for example, a voltage Vss is 0 V, for example, and a negative voltage Vn is −8 V, for example.
The voltage level shifter circuit as shown in
FIG. 14
has the following problems when an input signal Si transtions from a voltage Vcc to a voltage Vss.
When the input signal Si having a voltage Vss is input, the transistor N
1
is turned off. At this time, the transistor P
1
is in an off state, and therefore a voltage at a node nd
1
is kept at Vss Then, the transistor N
2
is turned on. At this time, the transistor P
2
is still in an on state, and therefore a through current flows through the transistors P
2
and N
2
.
A parasitic load is produced between a terminal T
5
to which a voltage Vss is applied and a node nd
2
. Accordingly, a voltage at a node nd
4
is increased. When the voltage at the node nd
4
rises to the value Vpp-Vthp
1
, the transistor P
1
will not be turned on. Vthp
1
herein refers to a threshold voltage for turning on the transistor P
1
.
As a result, the transistors P
2
and N
2
are kept in an on state, and a through current continues to flow through the transistors P
2
and N
2
. Accordingly, the voltage level shifter circuit of
FIG. 14
does not invert a voltage level.
The voltage level shifter circuit as shown in
FIG. 15
has the following problems when an input signal Si transtions from a voltage Vcc to a voltage Vss.
When the input signal Si transtions from a voltage Vcc to a voltage Vss, a voltage at the node nd
5
becomes Vcc. In this case, the transistor P
1
is kept in an off state, and therefore a voltage at a node nd
1
rises to the value Vcc-Vthn
1
. Vthn
1
refers to a threshold voltage for turning on the transistor N
1
.
Then, a voltage at the node nd
6
becomes Vss. Since the transistor P
1
is in an off state, the voltage at the node nd
1
is kept at the value Vcc-Vthn
1
. A voltage Vcc-Vthn
1
is a voltage which is equal to or lower than a voltage Vpp-Vthp
2
. Vthp
2
refers to a threshold voltage for turning on the transistor P
2
. Thus, the transistor P
2
is still in an on state, and therefore a through current flows through the transistor P
2
, the transistor N
2
, and a part of an inverter INV
3
. Actually, a parasitic resistance is produced between a node nd
2
and the terminal T
2
which receives a reference voltage Vss, and therefore a voltage at a node nd
4
rises. In the case where the voltage at the node nd
4
is equal to or higher than the voltage Vpp-Vthp
1
, the transistor P
1
is kept in an off state. Thus, the voltage at the node nd
1
is kept at the value Vcc-Vthn
1
, and therefore the transistor P
2
will not be turned off. As a result, a through current continues to flow through the transistor P
2
, the transistor N
2
, and a part of the inverter INV
3
. Accordingly, the voltage level shifter circuit as shown in
FIG. 15
does not invert a voltage level.
The voltage level shifter circuit as shown in
FIG. 16
has the following problems when an input signal Si transtions from a voltage Vcc to a reference voltage Vss.
When the voltage of the input signal transtions from a voltage Vss to a voltage Vcc, the transistor P
1
is first turned off.
At this time, the transistor N
1
is still in an on state, and a voltage at the node nd
11
is slightly lower than the voltage Vcc. Therefore, the transistor N
2
is kept in an on state. When the transistor P
2
is turned on thereafter, a through current flows through the transistors P
2
and N
2
. Accordingly, a voltage at a node nd
15
falls to a value lower than the voltage Vcc.
It is now assumed that a voltage at a node nd
12
falls to 1.5 V due to the influences of a parasitic load and the like. Then, a voltage at the back-gate of the transistor P
2
drops, significantly degrading the current driving capability of the transistor P
2
.
Because of a significantly high channel resistance of the transistor P
2
, a voltage at a node nd
14
falls to a value which is very close to a voltage Vn. It is noted that the voltage at the node nd
14
is determined by a ratio of the channel resistance between the transistors P
2
and N
2
.
In the case where the voltage at the node nd
14
is lower than the value Vn+Vthn
1
, the transistor N
1
will not be turned on. Vthn
1
herein refers to a threshold voltage for turning on the transistor N
1
. Since a voltage at the node nd
11
does not transition, the transistor N
2
will be kept in an on state. As a result, a
Lee Michael G.
Morrison & Foerster / LLP
Paik Steven S.
Sharp Kabushiki Kaisha
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