Voltage level shifter

Details Voltage level shifter Voltage level shifter

2000-03-03

2001-07-17

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S080000, C326S083000, C326S114000

Reexamination Certificate

active

06262598

ABSTRACT:

The present invention relates to a voltage level shifter. Such a shifter may, for example, be used in large area silicon-on-insulator (SOI) circuits for interfacing with signals of smaller amplitudes. An example of such an application is monolithic driver circuitry for flat-panel matrix displays, such as liquid crystal displays, fabricated with low temperature poly-silicon thin-film transistors (TFTs) where interfacing between signal levels of 3.3 to 5 volts and signals of 10 to 20 vlts is often required. Another application is in random access memories (RAM) for improving the response time of line sense amplifiers.
FIG. 1
of the accompanying drawings illustrates a basic CMOS inverter which may be used as a simple voltage level shifter. The inverter comprises a P-type transistor T
1
and an N-type transistor T
2
whose drains are connected together and whose sources are connected to a supply line vdd and ground gnd, respectively. The gates of the transistors T
1
and T
2
are connected together and to an input terminal IN and the drains of the transistors T
1
and T
2
are connected together to an inverting output !OUT. The input signals can swing about the inverter switch point between logic levels which are less than the voltages defined by the supply line vdd and ground gnd. The inverter can operate as a level shifter because the output swings between voltage levels which are almost equal to the voltages of the supply line vdd and ground gnd. However, in practice, the degree of level shifting is relatively small because voltages close to the inverter switch point result in simultaneous and undesirable conduction of the transistors T
1
and T
2
the condition for this not to occur is that:
|&Dgr;V
IN
|>VDD−V
Tn
−|V
Tp
|
where VDD is the voltage on the supply line vdd and V
Tn
and V
Tp
are the threshold voltages of the N-type and P-type transistors, respectively.
FIG. 2
of the accompanying drawings illustrates another type of single input level shifter for low input voltages, for example as disclosed in U.S. Pat. No. 4,707,623. The shifter comprises a first circuit branch comprising a first P-type transistor T
1
and a second N-type transistor T
2
with their drains connected together to an inverting output !OUT and their sources connected to a supply line vdd and ground gnd, respectively. The level shifter comprises a second circuit branch comprising third and fourth P-type transistors T
3
and T
4
. The source of the third transistor T
3
is connected to the supply line vdd whereas the drain of the fourth transistor T
4
is connected to ground gnd. The drain of the transistor T
3
is connected to the source of the transistor T
4
and to the gate of the transistor T
2
. An input IN is connected to the gates of the transistors T
1
and T
4
. A bias voltage input Vb is connected to the gate of the transistor T
3
. The transistors T
3
and T
4
are connected as a source follower whose output voltage is given by V
IN
+(VDD−Vb) when the transistors T
3
and T
4
are matched and are in saturation. The input signal drives the gate of the transistor T
1
directly whereas the output of the source follower drives the gate of the transistor T
2
with a copy of the input signal which is shifted in the positive direction by (Vdd−Vb). These voltage levels are sufficient to switch the transistors T
1
and T
2
, which operate as push-pull devices with high state logic input levels which are substantially lower than the supply voltage and low state logic input levels which are substantially equal to ground potential.
FIG. 3
illustrates the results of a simulation of the level shifter shown in
FIG. 2
used to shift a 0-5 volt input to a 15-0 volt output with the bias voltage input Vb connected to ground. For this simulation, all transistors are of equal size except the transistor T
2
which is of twice the width of the other transistors for correct operation. The output !OUT is loaded, in the simulation, with the input of an inverter of the type shown in FIG.
1
. The simulated transistor performance is similar to that which is achievable with low temperature poly-silicon TFT technology.
FIG. 3
illustrates the voltage levels of the input signal IN, the output signal !OUT and the supply voltage VDD. Also, the switching level of the inverter to which the output is simulated as being connected is illustrated. The output !OUT swings about the switch point of the inverter, in particular between values of 2.3 volts and 10.4 volts. However, because of the small voltage transitions at the output, the scaling of the transistors T
1
and T
2
has to be relatively precise in order to ensure a sufficient voltage swing about the inverter switch level. Also, this signal does not fully turn off at least one of the inverter transistors and this results in relatively high current consumption in the inverter.
FIG. 4
of the accompanying drawings illustrates a known type of CMOS sense amplifier of the type disclosed in A. Bellaouar and M. Elmasry, “Low-power Digital VLSI Design Circuits and Systems”, Kluwer Academic Publishers, 1995. The sense amplifier comprises second and sixth P-type transistors T
2
and T
6
and first, fifth and seventh N-type transistors T
1
, T
5
and T
7
. The transistors T
7
acts as a tail current source with its source connected to ground gnd and its gate connected to a bias voltage input Vb. The transistors T
1
and T
5
are connected as a long tail pair with their sources connected to the drain of the transistor T
7
and their gates connected to a first input IN for receiving direct input signals and a second input !IN for receiving inverted input signals. The drains of the transistors T
1
and T
5
are connected to outputs !OUT and OUT and to the drains of the transistors T
2
and T
6
, respectively. The sources of the transistors T
2
and T
6
are connected to the supply line vdd. The gate of the transistor T
2
is connected to the drain of the transistor T
6
whereas the gate of the transistor T
6
is connected to the drain of the transistor T
2
.
The sense amplifier thus has two differential inputs and two differential outputs. For the purpose of explaining operation of the amplifier, the transistors are assumed to be perfectly matched with identical input voltage levels supplied to the inputs so that the tail current flows in equal portions through the first circuit branch comprising the transistors T
1
and T
2
and the second circuit branch comprising the transistors T
5
and T
6
. This condition is meta-stable and changes in response to any perturbation of the differential input voltage. For example, if the voltage at the input IN is slightly larger than that at the inverting input !IN, the transistor T
1
turns on more than the transistor T
5
. This has the effect of lowering the voltage at the inverting output !OUT. The transistor T
6
is turned on more and this increases the voltage at the direct output OUT. The transistor T
2
is thus turned off further, which reduces the voltage at the ouput !OUT and increases the voltage at the output OUT. Thus, a slight imbalance in the voltages supplied to the inputs IN and !IN is sensed and amplified. However, the output voltages cannot swing between ground potential and the supply line potential because some tail current is always flowing.
FIG. 5
of the accompanying drawings illustrates an “inverted logic” version of the amplifier illustrated in FIG.
4
. In particular, the conduction types of the transistors are reversed and the supply voltage polarity is reversed. Such an arrangement is more useful for level-shifting the high logic state of the input with the low logic state of the input and output being at ground.
FIG. 6
of the accompanying drawings illustrates a simulation of the amplifier shown in
FIG. 5
with the same conditions as were used for the simulation of the shifter of
FIG. 2
illustrated in FIG.
3
. Initially, the direct input signal IN is low (so that the inverted input signal !IN is

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