Voltage generator methods and apparatus

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36518909, 365149, G11C 700, G11C 1604

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active

059462590

ABSTRACT:
A reduced threshold voltage (Vt) magnitude or depletion mode metal-oxide-semiconductor (MOS) capacitor capable of use in a charge pump circuit such as a substrate bias voltage generator in a dynamic random access memory (DRAM) integrated circuit. The Vt magnitude of a p-channel MOS field-effect transistor (FET) used as a capacitor is reduced by using the same ion-implantation step used to increase the Vt magnitude of an n-channel MOS FET. The Vt magnitude of an n-channel MOS FET used as a capacitor is reduced by using the same ion-implantation step used to increase the Vt magnitude of a p-channel MOS FET. By sufficiently reducing Vt magnitude, a depletion mode MOS capacitor is formed. Reduced Vt magnitude and depletion mode MOS capacitors increase the useful voltage range of the capacitor, optimizing operation at low supply voltages.

REFERENCES:
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patent: 4467450 (1984-08-01), Kuo
patent: 4667312 (1987-05-01), Doung et al.
patent: 5266821 (1993-11-01), Chern et al.
patent: 5665995 (1997-09-01), Hsue et al.
Streetman, B.G., "Solid State Electronic Devices", 3rd Edition, Prentice Hall Series in Solid State Physical Electronics, Nick Holonyak, Jr., Series Editor, (1990).

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