Method and system for storing and processing multiple memory add

Details Method and system for storing and processing multiple memory add Method and system for storing and processing multiple memory add

1998-10-07

1999-08-31

Phan, Trong

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523008, 36518905, G11C 1604, G11C 800

Patent

active

059462604

ABSTRACT:
A packetized dynamic random access memory ("DRAM") receives command packets each of which contain a plurality of command words. One of the command words in each command packet includes a column address. Each of the command words, including the column address, is stored in one of a plurality of storage units so that a plurality of column addresses may be simultaneously stored in the storage units. The column addresses are individually coupled from respective storage units to a common column address bus which includes an address latch. The column address bus drives a column address processing circuit, such as a column address decoder. Also included is an adder that allows the DRAM to operate in a burst mode. In response to receiving an increment signal, the adder increments the column address at the output of the column address bus and applies the incremented address to the input of the column address bus.

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