Voltage generation circuits and methods of operating same...

Details Voltage generation circuits and methods of operating same... Voltage generation circuits and methods of operating same...

2002-08-01

2004-02-17

Nguyen, Matthew V. (Department: 2838)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C363S059000

Reexamination Certificate

active

06693482

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-46567, filed Aug. 1, 2001, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit devices and methods of operating same and, more particularly, to integrated circuit memory devices and methods of operating same.
BACKGROUND OF THE INVENTION
A conventional integrated circuit memory device may include a high voltage generating circuit for generating a voltage higher than a power voltage. Devices using a battery as a power source may include a high voltage generating circuit for generating a voltage higher than a battery power voltage. A high voltage generating circuit of an integrated circuit memory device may generate a high voltage target of about 4 volts when an external power voltage is in a predetermined range, such as, for example, about 2.2 volts to about 2.8 volts.
As a level of a power voltage of a system incorporating an integrated circuit memory device is decreased, however, a level of an external power voltage applied to the integrated circuit memory device may also decrease. Accordingly, when an external power voltage less than, for example, about 2.2 volts is applied, the integrated circuit memory device's high voltage generating circuit may not be able to generate a target voltage of about 4 volts.
In more detail, the integrated circuit memory device's high voltage generating circuit may use a step-up capacitor having a specific side based on the assumption that an external power voltage is in a predetermined range. When an external power voltage falls below the expected voltage range, the high voltage generating circuit may generate a target voltage of about 4 volts by increasing the capacitance of the step-up capacitor. Unfortunately, increasing the size of the step-up capacitor may increase the layout area needed to accommodate the high voltage generating circuit.
A conventional high voltage generating circuit
100
will now be described with reference to FIG.
1
. Signals and the media carrying those signals may be referred to by the same names. Referring now to
FIG. 1
, the conventional high voltage generating circuit
100
comprises first and second delay circuits
10
and
12
, first and second level shifters
14
and
16
, NOR gates NOR
1
and NOR
2
, a NAND gate NA
1
, inverters I
1
through I
8
, NMOS transistors NC
1
through NC
5
, and NMOS transistors N
1
through N
7
.
An external power voltage VEXT is applied to the first and the second delay circuits
10
and
12
, the NOR gates NOR
1
and NOR
2
, the NAND gate NA
1
, and the inverters I
3
through I
6
. A high voltage VPP is applied to the inverters I
1
, I
2
, I
7
, and I
8
, and the first and second level shifters
14
and
16
.
The first and the second delay circuits
10
and
12
, the NOR gates NOR
1
and NOR
2
, the first and the second level shifters
14
and
16
, the NAND gate NA
1
, the inverters I
1
through I
8
, the NMOS capacitors NC
1
and NC
2
, and the NMOS transistors N
1
and N
2
comprise a circuit that generates control signals for controlling a voltage step-up operation of the high voltage generating circuit. The NMOS transistors N
3
, N
4
, and N
6
comprise a circuit that pre-charges signals n
8
, n
10
, and n
13
during a pre-charge operation. The NMOS capacitor NC
3
and the NMOS transistor N
5
comprise a first step-up circuit that steps-up the signal n
10
, which corresponds to a step-up node, during an active operation. The NMOS capacitor NC
4
comprises a second step-up circuit that steps-up the signal n
10
node during an active operation. The NMOS capacitor NC
5
comprises a step-up circuit that steps-up the signal n
13
during an active operation. The NMOS transistor N
7
comprises a high voltage transmission circuit that transmits the signal n
10
at the step-up node to a high voltage generation terminal during an active operation.
The first delay circuit
10
delays a pulse signal EN by a first delay time d
1
to generate a signal n
1
. The second delay circuit
12
delays an output signal of the first delay circuit
10
by a second delay time d
2
to generate a signal n
2
. The NOR gate NOR
1
NORs the pulse signal EN and the signal n
1
to generate a signal n
3
. The NOR gate NOR
2
NORs the signals n
2
and n
3
. The NAND gate NA
1
and the inverter I
6
AND the signals n
2
and n
3
. The first and the second level shifters
14
and
16
level-shift levels of the output signals of the NOR gate NOR
2
and the inverter I
6
, respectively. The inverter I
1
inverts an output signal of the first level shifter
14
to generate a signal n
4
. The inverter I
2
inverts an output signal of the inverter I
1
. The NMOS capacitor NC
1
pre-charges a signal n
5
to a level of the external power voltage VEXT in response to an output signal of the inverter I
2
. The NMOS transistor N
1
generates a signal n
5
at the external power voltage level VEXT in response to the signal n
4
. The inverter I
3
inverts the signal n
3
to generate a signal n
7
. The NMOS transistor N
2
generates a signal n
6
at the external power voltage level VEXT. The NMOS capacitor NC
2
pre-charges the signal n
6
to the external power voltage VEXT level in response to the signal n
3
. The NMOS transistor N
3
generates a signal n
8
at the external power voltage level VEXT in response to the signal n
3
. The NMOS capacitor NC
3
steps up the signal n
8
in response to the signal n
7
. The NMOS transistor N
5
facilitates charge sharing between nodes n
8
and n
10
to step up the signal n
10
in response to the signal n
5
. The NMOS transistor N
4
generates the signal n
10
at the external power voltage level VEXT in response to the signal n
6
. The inverters I
4
and I
5
delay the signal n
2
to generate a signal n
9
. The NMOS capacitor NC
4
steps up the signal n
10
in response to the signal n
9
. The inverter I
7
inverts an output signal of the second level shifter
16
to generate a signal n
11
. The inverter I
8
inverts the signal n
11
to generate a signal n
12
. The NMOS transistor N
6
generates the signal n
13
at the external power voltage level VEXT in response to the signal n
11
. The NMOS capacitor NC
5
steps up the signal n
13
in response to the signal n
12
. The NMOS transistor N
7
facilitates charge sharing between the node n
10
and the high voltage generation terminal in response to the signal n
13
.
FIG. 2
is a waveform diagram that illustrates operations of the conventional high voltage generating circuit
100
of FIG.
1
. During a time period t
1
, the external power voltage VEXT is applied and the pulse signal EN is at a common or ground voltage level VSS. The first delay circuit
10
delays the pulse signal EN by a first delay time d
1
to generate a signal n
1
at the ground voltage level VSS. The second delay circuit
12
delays the signal n
1
by a second delay time d
2
to generate a signal n
2
at the ground voltage level VSS. The NOR gate NOR
1
NORs the pulse signal EN and the signal n
2
to generate a signal n
3
at the external power voltage level VEXT. The NOR gate NOR
2
, the first level shifter
14
, and the inverter I
1
receive the signals n
2
and n
3
to generate the signal n
4
at the high voltage level VPP. The NMOS transistor N
1
pre-charges the signal n
5
to the external power voltage level VEXT in response to the signal n
4
. The inverter I
3
inverts the signal n
3
, which is at the external power voltage level VEXT, to generate the signal n
7
at the ground voltage level VSS. The NMOS transistor N
2
pre-charges the signal n
6
to the external power voltage level VEXT. The NMOS capacitor NC
2
steps up the signal n
6
to a voltage of 2VEXT when the signal n
3
is driven to the external power voltage level VEXT. The NMOS transistors N
3
and N
4
pre-charge the signals n
8
and n
10
to the external power voltage level VEXT, respectively, when their gate terminals are driven to a voltage level of 2VEXT. The inverters I
4
and I
5
generate th

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