Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-12-03
2004-02-03
Riley, Shawn (Department: 2838)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S226000
Reexamination Certificate
active
06687151
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-30206, filed in Feb. 7, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage generation circuit for selectively generating a voltage higher than a power supply voltage and a negative voltage on one node.
2. Description of the Related Art
FIG. 15
is a diagram showing a prior art 2T2C-type ferroelectric memory circuit.
A memory cell
1
consists of an NMOS transistor
2
and a ferroelectric capacitor CF
1
connected in series between a bit line BL and a plate line PL, and an NMOS transistor
3
and a ferroelectric capacitor CF
2
connected in series between a bit line /BL and the plate line PL. The control gates of the NMOS transistors
2
and
3
are connected to a word line WL. Each of the ferroelectric capacitors CF
1
and CF
2
consists of two opposite electrodes and a ferroelectric film inserted therebetween.
In a case writing a bit ‘1’ in this memory cell
1
, the following operation is performed.
The bit lines BL and /BL are set to the power supply voltage VDD and 0V, respectively, and the voltage of the word line WL is raised to turn on the NMOS transistors
2
and
3
. A positive pulse is supplied to the plate line PL to perform the following operation. When the plate line PL is at 0V, a polarization denoted by an arrow shown in
FIG. 15
is generated across the ferroelectric capacitor CF
1
. Thereafter, the plate line PL becomes the power supply voltage VDD, and a polarization denoted by another arrow which is the opposite direction to the polarization across the capacitor CF
1
is generated across the ferroelectric capacitor CF
2
. Then, the plate and word lines PL and WL return to 0V, and in this state, a residual polarization exists across each of the ferroelectric capacitors CF
1
and CF
2
.
In a case reading this data from the memory cell
1
, the following operation is performed.
The bit lines BL and /BL have been already precharged to 0V. The word line WL rises to a high, turning on the NMOS transistors
2
and
3
, and simultaneously the plate line PL rises to the power supply voltage VDD. This causes a transfer of charges from the ferroelectric capacitors CF
1
and CF
2
to the bit lines BL and /BL, raising the voltages of bit lines BL and /BL to the amount of &Dgr;VH and &Dgr;VHL, respectively. The rise of the plate line PL causes a reversal in the polarization of the ferroelectric capacitor CF
1
, but not in the polarization of the ferroelectric capacitor CF
2
. Therefore, the transferred charge of the ferroelectric capacitor CF
1
is larger than that of the ferroelectric capacitor CF
2
, resulting in &Dgr;VH>&Dgr;VL. A sense amplifier
4
is activated to amplify the voltage difference &Dgr;VH−&Dgr;VL, thereby bringing the bit lines BL and /BL to the power supply voltage VDD and 0V, respectively. The plate line PL falls to 0V, performing a restore operation in which the polarization of the ferroelectric capacitor CF
1
is reversed to return to the original state. The sense amplifier
4
becomes inactive, and the bit lines BL and /BL are set to 0V by a precharge circuit not shown in the figure. The word line WL falls to ‘L’ to turn off the NMOS transistors
2
and
3
.
However, when the power supply voltage VDD is lowered to, for example, 1.5V for reducing the power consumption, the amount of charges transferred to the bit lines BL and /BL is reduced, resulting in lowering the voltage difference &Dgr;VH−&Dgr;VL between the bit lines BL and /BL, and thereby increasing the possibility of reading errors.
To cope with this, if a voltage higher than the power supply voltage VDD or a negative voltage is applied to the plate line PL, instead of the power supply voltage VDD or 0V, respectively, the voltages applied to the ferroelectric capacitors CF
1
and CF
2
are raised and the voltage difference between the bit lines BL and /BL in reading operation, is raised, consequently reducing the possibility of reading errors.
However, as shown in
FIG. 16
, a negative-voltage generation circuit
5
and a high-voltage generation circuit
6
are separated in the prior art. Therefore, when the high voltage and the negative voltage are output through one output node NO (PL), it is necessary to connect the outputs of the negative-voltage generation circuit
5
and the high-voltage generation circuit
6
through an NMOS transistor
7
and a PMOS transistor
8
, respectively, to the output node NO, consequently complicating the configuration as explained below.
In such a configuration, when a control signal SC inputted to the control gates of the transistors
7
and
8
is low, the transistors
7
and
8
are OFF and ON, respectively, thereby applying a high voltage VH to the output node NO. On the other hand, when the control signal SC is high, the transistors
7
and
8
are ON and OFF, respectively, thereby applying a negative voltage VL to the output node NO.
However, both kinds of transistors exist in one chip: one kind thereof receiving a usual power supply voltage VDD, and the other kind thereof receiving a negative voltage VL. Therefore, in order not to allow a current to flow between the source and the back gate of the NMOS transistor
7
, the NMOS transistor
7
should be formed in a triple-well structure as shown in FIG.
17
(A) so that the back gate is reverse-biased. For this reason, the manufacturing process of the semiconductor chip becomes complicated, resulting in raising the cost. FIG.
17
(B) shows a vertical cross-sectional view of a usual CMOS, in which only a PMOS transistor is formed in twin-well structure and an NMOS transistor has a simple structure in comparison with the NMOS transistor
7
of FIG.
17
(A).
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a voltage generation circuit having normal transistors of simple structure.
In one aspect of the present invention, there is provided a voltage generation circuit for selectively generating a low voltage lower than a first power supply voltage and a high voltage higher than a second power supply voltage on an output node on the basis of the first and second power supply voltages, the second power supply voltage being higher than the first power supply voltage, the voltage generation circuit comprising:
a first PMOS transistor, having a current path and a control gate, a first end of the current path being connected to the output node, a back gate thereof being connected to a second end of the current path;
a first NMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the second end of the current path of the first PMOS transistor, a second end of the current path thereof being connected to the first power supply voltage;
a first capacitor, having first and second electrodes, the first electrode being connected to the output node;
a second PMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the output node, a back gate thereof being connected to a second end of the current path thereof, the control gate thereof being connected to the first power supply voltage;
a second NMOS transistor, having a current path and a control gate, a first end of the current path thereof being connected to the second end of the current path of the second PMOS transistor; and
a control circuit.
The control circuit:
raises the second electrode of the first capacitor to the second power supply voltage to step up the output node to the high voltage from a first state where the first and second NMOS transistors are OFF and where the output node and the second electrode of the first capacitor are at the second and first power supply voltages, respectively; and
lowers the second electrode of the first capacitor to the first power supply voltage to step down the output node to t
Endo Toru
Kawashima Shoichiro
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Riley Shawn
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