Voltage detecting circuit for semiconductor memory device

Details Voltage detecting circuit for semiconductor memory device Voltage detecting circuit for semiconductor memory device

2000-12-22

2002-09-24

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Powering

C365S189070, C365S189090

Reexamination Certificate

active

06456555

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to voltage detecting circuits for use in semiconductor memory devices, and more particularly, to a boosted voltage detecting circuit for detecting a stable boosted voltage level in semiconductor memory devices.
BACKGROUND OF THE INVENTION
High-capacity semiconductor memory devices, such as dynamic random access memories (DRAMs), utilize a low voltage power supply to decrease power consumption and increase reliability. In such devices, it is desirable to utilize a boosted voltage (VPP) to improve the transfer characteristics of certain circuits. For example, in order to ensure accurate and reliable operation of word line driver circuits, a boosted voltage VPP is used as the power supply voltage to drive word line voltages higher than the low voltage level of the low voltage power supply.
In a semiconductor memory device, a VPP generator is used to generate the boosted voltage VPP. The VPP generator includes a pumping circuit driven by an oscillator, and a VPP level detecting circuit that controls the operation of the oscillator. The VPP level detecting circuit detects the VPP level that is usually determined by the usage of the VPP voltage and compares it to a target VPP level. When the VPP level reaches the target level, the detecting circuit activates a detection signal that causes the oscillator to stop operating. This, in turn, causes the pumping circuit to stop pumping. While the pumping circuit is deactivated, as the VPP is used as a power source, the VPP voltage level drops. When the VPP voltage level drops below the target VPP level, the detecting circuit deactivates the detection signal, causing the pumping circuit to resume pumping.
When using a boosted voltage VPP, it is important to get an exact target level because an unnecessarily higher or lower VPP level than the target level may result in increased power consumption, increased stress to the device, and poor transistor performance. A precise and stable detecting circuit is therefore required.
A conventional VPP level detecting circuit of a semiconductor memory device is illustrated in FIG.
1
. Referring to
FIG. 1
, the detecting circuit includes a voltage generator
10
for generating a comparison voltage, and a driving circuit
20
for detecting a target VPP level and for generating a voltage level detection signal (DET). The voltage generator
10
includes serially-connected NMOS transistors
11
,
12
, and
13
. One end of the voltage generator
10
is coupled to a power supply voltage (VDD), and an opposite end is coupled to a ground voltage (VSS). A gate of transistor
12
is connected to the power supply voltage VDD, and gates of transistors
11
and
13
are connected to the boosted voltage VPP. The driving circuit
20
includes three inverters
21
,
22
, and
23
. An input of inverter
21
is connected to node A. Assuming that the equivalent resistance values of the source drain path of transistors
11
,
12
, and
13
, are R
1
, R
2
, and R
3
, respectively, then the voltage of node A can be expressed by the equation:
VA=VDD*{
(
R
2
+
R
3
)/(
R
1
+
R
2
+
R
3
)}.
As the boosted voltage VPP level increases, the resistance values of transistors
11
and
13
decrease because their gates are connected to the boosted voltage VPP. The resistance value of transistor
12
, however, remains almost unchanged because its gate is connected to the power supply voltage VDD, which has a specific and fixed value. As the boosted voltage VPP level increases, therefore, the voltage level of node A also increases.
A logic threshold voltage of a P-type MOS (PMOS) or an N-type MOS (NMOS) inverter is determined by its width/length ratio. An inverter starts to change its output state around the logic threshold voltage. If the voltage level of node A is higher than the logic threshold voltage level of inverter
21
, therefore, the voltage level detection signal DET, output from inverter
23
, becomes low and a pumping operation is stopped by the voltage level detection signal DET. If the voltage level of node A is lower than the logic threshold voltage, however, the voltage level detection signal DET becomes high and the pumping operation resumes. To implement the target VPP level detection operation, the voltage level of node A at the target VPP level may be adjusted to around the logic threshold voltage of inverter
21
by controlling the sizes of transistors
11
,
12
, and
13
, and the inverter
21
.
Unfortunately, the conventional detecting circuit described above has a number of drawbacks. Among other things, this detecting circuit is sensitive to process and temperature variations. The voltage of node A at the target VPP level and the logic threshold voltage of the inverter
21
, for instance, vary with process and temperature variations. It is also possible for process and temperature variations to cause these two voltages to be shifted in different directions from each other because the inverter
21
includes both PMOS and NMOS transistors, and the voltage generator
10
only includes NMOS transistors. Because of these problems, the target VPP level may not be able to be accurately detected.
Variation of the detected VPP level due to process and temperature variations is even more serious during the high voltage test mode (such as a burn-in test mode) in comparison to a normal operation mode (such as a normal read or write mode). Another problem during high voltage tests is that it is difficult to get a target VPP level suitable for a high voltage test mode since the resistance value of the voltage generator
10
is designed for the normal operation mode.
Finally, the voltage gain of node A resulting from responding to the variation of the VPP level is so small (0.1-0.2) that variation of the logic threshold voltage due to process and temperature variations can critically vary the detected VPP level. In other words, the variation of node A voltage resulting from responding to the variation of VPP is relatively so small in comparison to the variation of logic threshold voltage of inverter
21
due to the process and temperature variations that a precise detection operation cannot be implemented using the prior art configuration.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a voltage detecting circuit capable of precisely and reliably detecting a target voltage level.
It is another object of the invention to provide a voltage detecting circuit that is unaffected by process and temperature variations.
It is still another object of the invention to provide a voltage detecting circuit capable of detecting a target voltage level suitable for both a normal operation mode and a test mode in response to an operation mode signal.
In order to attain the above objects, according to one embodiment of the present invention, a voltage detecting circuit includes a first voltage generator coupled to a first power supply voltage to provide a reference voltage. A second voltage generator is coupled to a second power supply voltage to provide a comparison voltage. A differential amplifier receives both the reference voltage and the comparison voltage and amplifies a voltage difference between the reference and comparison voltages. A driving circuit receives the amplified difference voltage and generates a voltage level detection signal. The reference voltage generated in the first voltage generator is variable in response to an operation mode signal.
According to another aspect of this invention, the first voltage generator includes a first reference voltage generating circuit for providing a first reference voltage in response to the operation mode signal during a normal operation mode of a semiconductor memory device, and a second reference voltage generating circuit for providing a second reference voltage in response to the operation mode signal during a test mode of the semiconductor memory device. The first and second reference voltages are each provided to the differential amplifier as the reference vo

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