Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-04-12
2004-07-06
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C327S158000, C327S534000, C331S057000
Reexamination Certificate
active
06759875
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal clock generation circuit, and particularly, to a voltage controlled oscillation circuit, used in a phase locked (synchronization) circuit, and having an oscillation frequency adjusted by a bias voltage.
2. Description of the Background Art
In data communication or the like, in order to reproduce transferred data correctly, a necessity arises for recovery of a clock signal in synchronization with a clock signal used in data transmission (a reference clock signal) and then, restoration of the data according to the recovered clock signal. In order to recover a clock signal that exactly tracks in frequency such a reference clock signal, there is generally used a phase locked circuit such as a PLL (a phase locked loop) or DLL (a delayed locked loop).
FIG. 31
is a diagram schematically showing a configuration of a conventional PLL circuit. In
FIG. 31
, the conventional phase locked circuit (PLL circuit) includes: a voltage controlled oscillation circuit (VCO)
900
having an oscillation frequency controlled by a control voltage VC to generate a recovered dock signal RCLK; a phase comparison circuit
904
comparing in phase recovered clock signal RCLK outputted by voltage controlled oscillation circuit
900
and a reference clock signal CLK with each other to generate a signal corresponding to a phase difference; and a charge pump
906
performing a charge/discharge operation according to a phase difference indicating signal from phase comparison circuit
904
to generate control voltage VC and apply control voltage VC to voltage controlled oscillation circuit
900
. Charge pump
906
includes a loop filter to remove a high frequency component of an output thereof and generate control voltage VC.
In the PLL circuit shown in
FIG. 31
, a negative feedback closed loop is constituted of voltage controlled oscillation circuit
900
, phase comparison circuit
904
and charge pump
906
, and control voltage VC is adjusted by phase comparison circuit
904
such that a phase difference becomes
0
(zero) between recovered clock signal RCLK and reference clock signal CLK and accordingly the oscillation frequency of voltage controlled oscillation circuit
900
is adjusted. By utilization of a negative feedback of the closed loop, correct frequency tracking can be performed on reference clock signal CLK to generate recovered clock signal RCLK.
FIG. 32
is a diagram showing an example of a configuration of voltage controlled oscillation circuit
900
shown in FIG.
31
. Voltage controlled oscillation circuit
900
shown in
FIG. 32
is a ring oscillator type voltage controlled oscillation circuit.
In
FIG. 32
, voltage controlled oscillation circuit
900
includes: a bias voltage generation circuit
900
a
for generating bias voltages VC
1
and VC
2
according to control voltage VC; and an oscillation circuit
900
b
having an oscillation frequency controlled by bias voltages VC
1
and VC
2
. Oscillation circuit
900
b
includes delay circuits D
1
to Dn cascaded in plural stages. An output signal OUT (recovered clock signal RCLK) is generated from delay circuit Dn at the final stage. The output signal of delay circuit Dn at the final stage is fed back to delay circuit D
1
at the first stage. Delay circuits D
1
to Dn are connected in a ring shape to constitute a ring oscillator.
Bias voltage generation circuit
900
a
includes: a P channel MOS transistor M
2
connected between a power supply node and an internal node AN, and having a gate connected to internal node AN; an N channel MOS transistor (insulated gate field effect transistor) M
1
connected between node AN and a ground node, and receiving control voltage VC at the gate thereof, a P channel MOS transistor M
3
connected between the power supply node and an internal node BN, and having a gate connected to internal node AN; and an N channel MOS transistor M
4
connected between internal node BN and the ground node, and having a gate connected to internal node BN. MOS transistors M
2
and M
3
constitutes a current mirror circuit, wherein MOS transistor M
2
serves as a master transistor, while MOS transistor M
3
serves as a slave transistor. Bias voltage VC
1
is generated at the gates of MOS transistors M
2
and M
3
. MOS transistor M
4
has the gate and drain connected to each other and has the gate voltage set according to the drain current thereof. That is, the gate and drain voltages of MOS transistor M
4
are determined such that a discharge current of MOS transistor M
4
and a supply current of MOS transistor M
3
are in balance with each other. Bias voltage VC
2
is generated at the gate and drain of MOS transistor M
4
.
In oscillation circuit
900
b
, each of delay circuits D
1
to Dn is of the same configuration as is the others and therefore, reference numerals are attached to components of delay circuit Dn at the final stage as a representative. Delay circuit Dn includes: P channel MOS transistors MC
1
and MC
5
connected in series between a power supply node and an internal output node; and N channel MOS transistors M
6
and MC
2
connected in series between the internal output node and a ground node. Bias voltages VC
1
and VC
2
are applied to the gates of respective MOS transistors MC
1
and MC
2
. An output signal of delay circuit (D(n-
1
)) at the stage previous to the final stage is applied to the gates of MOS transistors M
5
and M
6
at the final stage.
By applying bias voltages VC
1
and VC
2
to MOS transistors MC
1
and MC
2
, drive current amounts of MOS transistors MC
1
and MC
2
are set. MOS transistors MC
1
and M
2
constitute a current mirror circuit and MOS transistors MC
2
and M
4
constitute another current mirror circuit. In a case where each of the MOS transistors M
3
, M
4
, MC
1
and MC
2
has the same transistor size as others, currents of the same magnitude flow through the respective MOS transistors M
3
, M
4
, MC
1
and MC
2
.
When a voltage level of control voltage VC rises, a conductance of MOS transistor M
1
increases to increase a current amount flowing to the ground from MOS transistor M
2
through MOS transistor M
1
. A mirror current of a current supplied by MOS transistor M
2
is generated by MOS transistor M
3
and supplied to MOS transistor M
4
. A voltage level of internal node AN is the level at which a current amount that MOS transistor M
2
supplies and a current amount that MOS transistor M
1
discharges are in balance with each other. Likewise, a voltage of internal node BN is the level at which a current amount that MOS transistor M
3
supplies and a current amount that MOS transistor M
4
discharges are in balance with each other.
Therefore, when control voltage VC rises, a voltage level of node AN lowers and a voltage level of bias voltage VC
1
drops, while a voltage level of node BN rises and bias voltage VC
2
rises. With such bias voltage levels, in each of delay circuits D
1
to Dn of oscillation circuit
900
b
, a drive current amount of MOS transistor MC
1
increases and a drive current of MOS transistor MC
2
increases. Therefore, operating currents of delay circuits D
1
to Dn increases to cause operating speeds of delay circuits D
1
to Dn to be faster and increase an oscillation frequency of oscillation circuit
900
b.
On the other hand, when control voltage VC lowers, a conductance of MOS transistor M
1
decreases to decrease a drive current amount thereof. In response, a supply current of MOS transistor M
2
decreases to raise a voltage level of internal node AN. With increase of the voltage level at internal node AN, a voltage level of bias voltage VC
1
rises and drive current amounts of MOS transistors MC
2
and MC
4
is reduced and therefore, a voltage level of bias voltage VC
2
lowers.
Accordingly, operating current amounts of delay circuits D
1
to Dn of oscillation circuit
900
b
decrease, a delay time is longer; therefore, oscillation frequency of oscillation circuit
900
b
decreases.
Control voltage VC is at a voltage level corresponding to a pha
Mano Ryuji
Notani Hiromi
Chang Daniel D.
McDermott & Will & Emery
Renesas Technology Corp.
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