Voltage-controlled delay line with reduced timing errors and...

Details Voltage-controlled delay line with reduced timing errors and... Voltage-controlled delay line with reduced timing errors and...

2003-06-10

2004-06-29

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S158000, C327S161000, C327S237000, C327S270000

Reexamination Certificate

active

06756818

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a voltage-controlled delay line. More specifically, the present invention discloses a voltage-controlled delay line with an improved interconnection among delay cells for reducing timing errors and jitters.
2. Description of the Prior Art
Processing, exchanging, and distributing digital information exists in a broad spectrum of fields. For example, digital devices such as mobile phones, personal digital assistants (PDAs), information applicants (IAS) that are connected to a computer network, and personal computers are utilized to conveniently handle digital information. When the digital device processes, exchanges, and distributes digital information, the digital device requires triggers generated from a clock signal to process digital data that are sequentially transmitted. For instance, a central processing unit (CPU) of a personal computer coordinates data transmitted among digital circuits and data processed among the digital circuits with the help of triggers generated from a clock signal. In addition, with regard to a mobile phone, a clock signal is necessary to let the mobile phone correctly transmit and receive wireless signals. Suppose that the mobile phone functions as a receiver to receive incoming digital signals. In the beginning, the mobile phone has to establish a local clock signal synchronized with a timing associated with the incoming digital signals outputted from a base station. Therefore, the mobile phone successfully transmits wireless signals to the base station and correctly receives wireless signals outputted from the base station according to the local clock signal synchronized with clock signal used by the base station.
During a digital information processing procedure triggered by clock signals, a well-known technique for generating a synchronous clock signal based on a reference clock signal is widely adopted. In digital circuits, a frequency associated with one of two synchronous clock signals is multiplied or divided to further obtain two synchronous clock signals with different frequencies for conveniently handling digital data. In addition, it is possible to generate a synchronous clock signal with a greater driving capacity according to a reference clock signal. With regard to a digital mobile communication system, when a mobile phone, which functions as a receiver, needs to establish a local clock signal according to timing of received signals, the received signals have weak amplitudes so that the driving capacity of the received signals is poor. Therefore, a synchronous clock having a greater driving capacity and corresponding to timing of received signals is necessary to drive the mobile phone to work properly.
A circuit, which is capable of generating a synchronous clock signal according to a reference clock signal, is called a phase lock loop (PLL). One embodiment of the prior art PLL is a so-called delay lock loop (DLL). Please refer to
FIG. 1
, which is block diagram of a prior art DLL
10
. The DLL
10
has a clock generator
11
, a voltage-controlled delay line
12
, a phase detector
14
, a charge pump
16
, and two differential-to-single-ended converters
18
a
,
18
b
. The clock generator
11
simultaneously outputs a first reference clock signal CLK_REF+ and a second reference clock signal CLK_REF−, where a phase difference between the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF− is equal to 180 degrees. That is, the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF− are out of phase. The voltage-controlled delay line
12
, therefore, respectively delays the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF− to generate a first delay clock signal CLK_DL+ and a second delay clock signal CLK_DL−. The differential-to-signal-ended converter
18
a
outputs a first comparison signal CLK
1
based on a magnitude difference between the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF−. A period of the first comparison signal CLK
1
is identical to a period of the first reference clock signal CLK_REF+, and the period of the first comparison signal CLK
1
is identical to a period of the second reference clock signal CLK_REF− as well. Similarly, the differential-to-single-ended converter
18
b
outputs a second comparison signal CLK
2
based on a magnitude difference between the first delay clock signal CLK_DL+ and the second delay clock signal CLK_DL−.
A period of the second comparison signal CLK
2
is theoretically identical to a period of the first delay clock signal CLK_DL+, and the period of the second comparison signal CLK
2
is identical to a period of the second delay clock signal CLK_DL− as well. Then, the phase detector
14
judges if the first delay clock signal CLK_DL+ and the first reference clock signal CLK_REF+ are in phase according to phases of the first comparison signal CLK
1
and the second comparison signal CLK
2
. In addition, the phase detector
14
also judges if the second delay clock signal CLK_DL− and the second reference clock signal CLK_REF− are in phase according to phases of the first comparison signal CLK
1
and the second comparison signal CLK
2
. When either rising edges or falling edges of the first delay clock signal CLK_DL+ and the first reference clock signal CLK_REF+ differ by an integral multiple of the period of first reference clock signal CLK_REF+, the first delay clock signal CLK_DL+ and the first reference clock signal CLK_REF+ are in phase. Similarly, when either rising edges or falling edges of the second delay clock signal CLK_DL− and the second reference clock signal CLK_REF− differ by an integral multiple of the period of second reference clock signal CLK_REF−, the second delay clock signal CLK_DL− and the second reference clock signal CLK_REF− are in phase.
After the phase detector
14
compares phases of the first reference clock signal CLK
1
and the second reference clock signal CLK
2
, the phase detector
14
outputs control signals UP, DOWN to the charge pump
16
according to the reference clock signal CLK
1
leading the second reference clock signal CLK
2
or the reference clock signal CLK
1
lagging the second reference clock signal CLK
2
. After the charge pump
16
receives the control signal DOWN, the charge pump
16
raises voltage level of a control voltage Vpump. With regard to voltage-controlled delay line
12
, the increased control voltage Vpump drives the voltage-controlled delay line
12
to delay the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF− through a longer delay time. On the other hand, after the charge pump
16
receives the control signal UP, the charge pump
16
lowers voltage level of the control voltage Vpump. With regard to voltage-controlled delay line
12
, the decreased control voltage Vpump drives the voltage-controlled delay line
12
to delay the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF− through a shorter delay time.
Please refer to FIG.
2
and FIG.
3
.
FIG. 2
is a first timing diagram illustrating a phase lock process, and
FIG. 3
is a second timing diagram illustrating the phase lock process. Within FIG.
2
and
FIG. 3
, the waveforms from top to bottom respectively represent the first comparison signal CLK
1
, the second comparison signal CLK
2
, the control signal UP, the control signal DOWN, and time. For example, the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REF−, which correspond to the first comparison clock CLK
1
, are inputted into the voltage-controlled delay line
12
at time t1. The voltage-controlled delay line
12
outputs the first delay clock signal CLK_DL+ and the second delay clo

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