Voltage boosting circuit for semiconductor device

Details Voltage boosting circuit for semiconductor device Voltage boosting circuit for semiconductor device

2000-04-26

2001-07-17

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000, C327S543000

Reexamination Certificate

active

06262621

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly to a semiconductor device having a voltage boosting circuit for generating voltages that exceed the power supply voltage.
BACKGROUND OF THE INVENTION
Voltage boosting circuits are useful in semiconductor devices which often boost signal lines above power supply voltage VCC. For example, programming of non-volatile memory devices or read-write operation of dynamic random memory devices boosts word lines of the devices above power supply voltage.
FIG. 1
illustrates a voltage boosting circuit
1
of a known semiconductor device. This is disclosed in U.S. Pat. No. 5,796,293 (the '293 patent), entitled “VOLTAGE BOOSTING CIRCUITS HAVING BACKUP VOLTAGE BOOSTING CAPABILITY,” which is incorporated herein by reference in its entirety. As disclosed in the '293 patent, a main voltage boosting circuit
1
a
and a backup voltage boosting circuit
1
b
constitute voltage boosting circuit
1
. Main voltage boosting circuit
1
a
drives a signal voltage VPP when a semiconductor device including voltage boosting circuit
1
is in a standby mode, and backup voltage boosting circuit
1
b
drives signal voltage VPP when the semiconductor device is in an active mode. Operation of each component illustrated in
FIG. 1
is fully explained in the '293 patent, and thus is briefly described herein.
Main voltage boosting circuit
1
a
includes a first voltage level detector
15
that generates a predetermined output VPPOSCE, an oscillator
16
that generates an internal driver signal VPPDRV, and a main pump that provides a voltage boost to a signal line that carries signal voltage VPP in response to a rising edge of internal driver signal VPPDRV. Backup voltage boosting circuit
1
b
includes a control signal generator
13
that responds to a clock signal PR, a second voltage level detector
18
that triggers at a voltage level greater that a predetermined reference potential at which first detector
15
is set, a latch
19
that generates a latch signal PNAKE, a first pulse generator
21
that generates a first pulse PAKEF, a first active kicker that provides a voltage boost to the signal line that carries signal voltage VPP in response to a rising edge of first pulse PAKEK. Backup voltage boosting circuit
1
b
further includes a delay circuit
20
that generates a signal PNAKED, a second pulse generator
22
that generates a second pulse PAKES, and a second active kicker
24
that provides a voltage boost to the signal line that carries signal voltage VPP in response to a rising edge of second pulse PNAKED.
FIG. 2
is a circuit diagram of a second detector (or an independent level detector)
18
of FIG.
1
. Second detector
18
generates a logic high signal at a node
69
if signal voltage VPP drops below a target boost voltage. Output of an inverter
61
is then latched and held at each rising edge of a signal PVPPLATCH which is slightly delayed relative to the rising edge of a master clock signal PR. Accordingly, if signal voltage VPP is below the target boost voltage which second detector
18
is set to trigger, an output VPPDETA changes from low to high and remains high until signal voltage VPP is boosted above the target boost voltage.
In reliability testing of semiconductor devices, an externally applied power supply voltage (hereinafter, referred to as “an external power supply voltage”) is applied to the devices. When the external power supply voltage decreases below a specific voltage for operating the devices, an internal VCC generator produces and maintains an internal power supply voltage VCC. In contrast, when the external power supply voltage increases above the specific voltage, internal power supply voltage VCC also may rise proportionally to the increase of the external power supply voltage. The latter case can cause a problem in second detector
18
as described below.
Referring to
FIG. 2
, as internal power supply voltage VCC increases, current flowing through an NMOS transistor
57
increases because the gate of NMOS transistor
57
is tied to internal power supply voltage VCC. Accordingly, the potential of a node N
1
, which is a common gate of PMOS and NMOS transistors
59
and
60
, decreases as internal power supply voltage VCC increases. Then, output VPPDETA continues to remain high until voltage of signal line VPP is boosted above the target boost voltage. Thus, backup voltage boosting circuit
1
b
of
FIG. 1
boosts signal voltage VPP until output VPPDETA changes from high to low.
Furthermore, because the gate of an NMOS transistor
58
is coupled to a signal line (not shown) that sends signal voltage VPP, the potential of node N
1
decreases as signal voltage VPP increases. Then, backup voltage boosting circuit
1
b
of
FIG. 1
further boosts signal voltage VPP even though signal voltage VPP is already above the target boost voltage. Accordingly, signal voltage VPP increases exponentially as internal power supply voltage VCC or the external power supply voltage increases.
The exponential increase of signal line voltage VPP may deteriorate electric characteristics of MOS transistors coupled to the signal line that sends signal voltage VPP. For example, gate oxide layers of the transistors may breakdown because of high electric field across the layers. Therefore, a semiconductor device having voltage boosting circuit
1
of
FIG. 1
can have reduced lifetime and reliability.
SUMMARY OF THE INVENTION
A voltage boosting circuit includes a voltage detector, an active kicker controller, and an active kicker. The voltage detector receives a signal to be boosted and a clock signal and generates a detection signal after determining whether a potential of the signal to be boosted is higher than a target voltage level. The active kicker controller receives the detection signal and the clock signal and generates an active kicker control signal in response to the detection signal and the clock signal. The active kicker drives the signal to be boosted in response to the active kicker control signal.
The voltage detector includes a current source, a number of switching devices, a current compensating circuit, and an inverter circuit. The inverter circuit outputs the detection signal. The current compensating circuit provides a compensating current proportional to a power supply voltage. The current compensating circuit connects to the current source and includes switching devices and optional devices. The switching devices are MOS transistors.


REFERENCES:
patent: 5530395 (1996-06-01), Ting
patent: 5742197 (1998-04-01), Kim et al.
patent: 5757714 (1998-05-01), Choi et al.
patent: 5796293 (1998-08-01), Yoon et al.

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