VMOS ROM Array

Static information storage and retrieval – Systems using particular element – Semiconductive

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Details

3072388, 365174, G11C 1140

Patent

active

042636639

ABSTRACT:
An IGFET ROM array and method. A high density ROM array and method for its fabrication is disclosed. The memory array is formed of a plurality of VMOS transistors arranged in a matrix. A plurality of spaced apart diffused regions are formed on the surface of an epitaxial layer overlying a heavily doped substrate. V-grooves, oriented along the diffused regions, extend through the epitaxial layer dividing each diffused region into two electrically separate bit lines. Along the edge of the V-groove the substrate forms a source, the epitaxial layer forms the channel, and the bit line forms the drain of each of the plurality of transistors. An insulator layer is formed on the surface of the V-groove and is overlaid by spaced apart conductive word lines running orthogonal to the diffused bit lines. The conductive word lines form the gate electrodes for MOS transistors formed on each side of the V-groove. The ROM array is programmed by selectively ion implanting localized regions through the diffused bit line and into the epitaxial layer prior to the formation of the V-groove. The localized region act to increase the doping in the channel region to selectively form "off" devices. By forming the localized programming regions prior to the forming of the V-grooves, alignment restrictions are relaxed allowing for a higher density array.

REFERENCES:
patent: 4109270 (1978-08-01), von Basse et al.
patent: 4126881 (1978-11-01), von Basse et al.

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