Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1980-12-22
1983-01-25
Rutledge, L. Dewayne
Metal working
Method of mechanical manufacture
Assembling or joining
29576E, 29580, 29591, 148175, 148187, H01L 2120
Patent
active
043695647
ABSTRACT:
A semiconductor memory device is provided comprised of an integrated array of cells formed on a substrate in conjunction with parallel spaced-apart bit lines and conductive word lines that are perpendicular to the bit lines. A plurality of V-shaped recesses are located between and extend perpendicular to adjacent parallel bit lines. Two cells share each recess and each cell includes a VMOS transistor formed by one end portion of the recess and an isolated buried source region located under the adjacent bit line. A channel stop region is located between and isolates the VMOS transistors and their respective buried source regions at opposite ends of each recess. Thus, the VMOS pass gate is shared between adjacent bit lines and bit line capacitance is minimized. Also, the VMOS pass gates are self-aligned to eliminate alignment tolerances and minimize bit line capacitance. The invention also includes an efficient method for producing a semiconductor memory device with such an array of cells.
REFERENCES:
patent: 4003036 (1977-01-01), Jenne
patent: 4012757 (1977-03-01), Koo
patent: 4105475 (1978-08-01), Jenne
patent: 4109270 (1978-08-01), von Basse et al.
patent: 4116720 (1978-09-01), Vinson
patent: 4126881 (1978-11-01), von Basse et al.
patent: 4214312 (1980-07-01), Amir
American Microsystems, Inc.
Caserza Steven F.
Franklin Richard
MacPherson Alan H.
Rutledge L. Dewayne
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