VLSIC patterning process

Details VLSIC patterning process VLSIC patterning process

1998-03-20

2000-02-22

Huff, Mark F.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430313, 430317, 216 41, 216 48, 216 67, 216 79, 216 80, 427 96, 427145, 438712, 438723, G03F 720, H01L 21027

Patent

active

060278617

ABSTRACT:
A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses high resolution DUV photolithography. By using a thin layer of photoresist to pattern a hardmask, full advantage of the high resolution can be attained. The hardmask in turn, is sufficiently durable to withstand subsequent etching of the insulative layer. The methods taught by this invention are of particular value for the formation of contacts to semiconductive devices although they are also applied to forming via openings. DUV photoresists having thicknesses of less than 500 nm are used with a DUV stepper. The hardmask materials include Ti/TiN and amorphous silicon. Etching selectivities of these materials with respect to typical insulative materials used in integrated circuit manufacture are of the order of 50:1.

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patent: 4808259 (1989-02-01), Jillie, Jr. et al.
patent: 4915779 (1990-04-01), Srodes et al.
patent: 5468342 (1995-11-01), Nulty et al.
"Silicon Processing for the VLSI Era--vol. 1" Lattice Press, Sunset Beach, CA, 198, p463.

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