VLSI test circuit apparatus and method

Details VLSI test circuit apparatus and method VLSI test circuit apparatus and method

1997-09-19

1999-07-06

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

059205750

ABSTRACT:
An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.

REFERENCES:
patent: 4277699 (1981-07-01), Brown et al.
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4961013 (1990-10-01), Obermeyer, Jr. et al.
patent: 4961031 (1990-10-01), Naksgawa et al.
patent: 5323403 (1994-06-01), Elliott
patent: 5491699 (1996-02-01), Scheuermann et al.

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