VLSI dynamic memory

Details VLSI dynamic memory VLSI dynamic memory

1985-09-11

1988-12-13

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Semiconductive

357 22, G11C 1134, H01L 2980

Patent

active

047916117

ABSTRACT:
The disclosed chip is suitable for VLSI dRAMS. The memory cell includes a bipolar transistor, a JFET, and a capacitor. The capacitor comprises a MOSFET which is operated only in the accumulation mode. Each cell requires only three lines. On a p-substrate, which comprises the collector of the bipolar, the cell layers are:- an n-well which comprises the channel of the JFET and the base of the bipolar; a p-region, which comprises the gate of the JFET, the emitter of the bipolar, and the bottom plate of the capacitor; an oxide layer; and a conducting layer; arranged as a vertical stack in that order. The latter two layers are the insulator and the top plate of the capacitor. The source and drain of the JFET are respective n+ regions placed one either side of the stack. The n-well can be deep and hence can be compatible with conventional CMOS technology. The chip has full read, write, and refresh capability; is relatively easily manufactured; and can be considerably scaled down without losing performance.

REFERENCES:
patent: 4090254 (1978-05-01), Ho et al.
R. A. Carballo et al., "High Performance/Density Dynamic RAM Cell", IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, pp. 3227-3228.

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