VLSI device with global planarization

Details VLSI device with global planarization VLSI device with global planarization

1994-11-16

1995-09-19

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257758, 257759, 257752, H01L 2352, H01L 218234

Patent

active

054518040

ABSTRACT:
A new method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the silicon substrate and within the trenched isolation regions. Source and drain regions are formed within the silicon substrate wherein the top surfaces of the trenched isolation regions, the trenched polysilicon gate electrodes, and source and drain regions form a planarized top surface of the silicon substrate. A pre-metal dielectric layer is deposited over the planarized top surface. Contact openings are formed by etching through the dielectric to the trenched polysilicon gate electrodes and to the source and drain regions. The contact openings are filled with tungsten plugs wherein the top surfaces of the pre-metal dielectric and the tungsten plugs form a planarized top surface of the silicon substrate. A first metal layer is deposited over the planarized top surface. Oxygen ions are implanted into the first metal layer whereby the first metal layer is transformed into an insulator layer except where the layer is covered by photoresist wherein the top surface of the first metal layer forms a planarized top surface of the silicon substrate. The inter-metal dielectric layer and second metal layer are deposited, patterned, and planarized as for the pre-metal dielectric and first metal layers. A passivation layer completes fabrication of the integrated circuit.

REFERENCES:
patent: 3665265 (1972-05-01), Fujimoto
patent: 4333226 (1982-06-01), Abe et al.
patent: 4389481 (1983-06-01), Poleshuk et al.
patent: 4617193 (1986-10-01), Wu
patent: 4764484 (1988-08-01), Mo
patent: 4814285 (1989-03-01), Matlock et al.
patent: 4962058 (1990-10-01), Cronin et al.
patent: 5063175 (1991-11-01), Broadbent
patent: 5275973 (1994-01-01), Gelatos
patent: 5294562 (1994-03-01), Lur et al.
patent: 5308786 (1994-05-01), Lur et al.
patent: 5366925 (1994-11-01), Lur et al.
patent: 5372968 (1994-12-01), Lur et al.
patent: 5380671 (1995-01-01), Lur et al.
"An Advanced Four Level Interconnect Enhancement Module for 0.9 Micron CMOS" by C. A. Bollinger et al., VMIC Conf. Proceedings, Jun. 12-13, 1990, c. 1990 by IEEE, pp. 21-27.
VLSI Technology, International Edition, by SMSZE, McGraw-Hill Book Company, N.Y., N.Y., c 1988 by McGraw-Hill Book Co., pp. 473-474.
"Simulation of Sub-0.1-.mu.m MOSFET's with Completely Supressed Short-Channel Effect" by J. Tanaka et al., IEEE Electron Dev. Letters, vol. 14, No. 8, Aug. 1993, pp. 396-399.
"A New 0.25 .mu.m Recessed-Channel MOSFET with Selectively Halo-Doped Channel and Deep Graded Source/Drain" by W. H. Let et al., IEEE Electron Device Letters, vol. 14, No. 12, Dec. 1993, pp. 578-580.

Affiliated with

Also associated with

Rating

VLSI device with global planarization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with VLSI device with global planarization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and VLSI device with global planarization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1829971