VLSI chip macro interface

Details VLSI chip macro interface VLSI chip macro interface

1999-08-13

2002-10-15

Dharia, Rupal (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S117000, C710S305000

Reexamination Certificate

active

06467001

ABSTRACT:

TECHNICAL FIELD
The present invention relates to Very Large Scale Integrated (VLSI) circuit devices and particularly to a method and system for interconnection of macros in VLSI chips.
BACKGROUND ART
VLSI semiconductor circuit devices typically define complex systems including an extremely great number of circuits and multiple functional macros. The term circuit designates an entity consisting of one or two cells or areas of silicon containing circuit components. Due to the complexity and the great number of circuit components that must be contained on a semiconductor substrate in a VLSI device (chip), the design of such devices is a complex, expensive and time consuming activity. The component locations and the metallization connections for each unit must be individually designed to obtain maximum utility of the area of the semiconductor substrate for the circuits implemented on a particular substrate.
In chip design it is increasingly common to use predesigned functional macros and to combine them together in the development of new chips. The term macro designates an entity consisting of many cells arranged for a particular function, such as a CPU core or a memory controller. In the design of a new chip, one or more macros may be used. These macros may have been previously designed and tested and may even have been used in existing chips.
However the interface between these macros can be as complex as the designs themselves, and the benefit of using the macros can be eroded by the amount of time and effort taken to understand the interface, particularly when the designer of the new chip is different from the designer of the macros used, or when macros from several previous different projects are connected together.
FIG. 1
shows an example of four macros connected together according to the state of the art method. Each macro may need to be connected to each other; when the number of macros increases or when the interfaces between the macros are complex, the connection may become a “spaghetti junction” of wiring, making integration, timing and simulation of a chip very difficult and not completely reliable. Furthermore, priority problems may arise when two or more macros try to establish a connection with the same other macro. A more structured design is desirable, which provides higher performances and allows new macros to be designed and tested concurrently.
The present invention has the object to overcome the above drawbacks.
SUMMARY OF THE INVENTION
According to the invention we provide a method for interconnecting a plurality of macros in a VLSI chip, each macro representing at least one function of the chip, each macro having input/output signals according to a predetermined interface, the plurality of macros including at least one master and at least one slave, the at least one master being capable to request connection to the at least one slave, the method comprising the step of:
connecting the plurality of macros to an interconnect macro, the interconnect macro having input/output signal according to said predetermined interface, the interconnect macro connecting the at least one master to the at least one slave, allowing concurrent slave are connected to the interconnect macro.
Furthermore, according to the present invention we provide, in VLSI chip comprising a plurality of macros, each macro representing at least one function of the chip, each macro having input/output signals according to a predetermined interface, the plurality of macros including at least one master and at least one slave, the at least one master being able of requesting a connection to the at least one slave, an interconnect macro having input/output signals according the predetermined interface, the interconnect macro comprising:
means for connecting to the plurality of macros;
means responsive to a request from the at least one master, for establishing a connection between the at least one master and at least one slave, allowing concurrent communications when more than one master and more than one slave are connected to the interconnect macro.


REFERENCES:
patent: 5619661 (1997-04-01), Crews et al.
patent: 2 263 047 (1993-07-01), None
patent: 2 326 065 (1998-12-01), None
IBM Technical Disclosure Bulletin, vol. 38, No. 6, Jun. 1995, pp. 375-378.

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