Viterbi decoder with enhanced test function

Details Viterbi decoder with enhanced test function Viterbi decoder with enhanced test function

1999-03-02

2003-01-07

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S224000, C375S262000

Reexamination Certificate

active

06504881

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated viterbi decoder circuit and, more particularly to a viterbi decoder having enhanced test function.
BACKGROUND OF THE INVENTION
A viterbi decoder is used to decode encoded convolutional codes using a maximum likelihood method. The decoder selects a path of a code sequence, which is most likely to be the received code sequence, from among a plurality of known code sequences. The decoder therefore obtains the decoded data which corresponds to the selected path. Viterbi decoders are used, for example, for error correction in satellite communication systems.
The principles of viterbi decoding are described, for example, in “CDMA Principles of Spread Spectrum Communication” by A. J. VITERBI, ADDISON-WESLEY PUBLISHING COMPANY, pp. 132-138, April, 1995. A viterbi decoder is discussed in U.S. Pat. No. 4,614,933.
FIG. 1
shows a block diagram of a conventional viterbi decoder. The viterbi decoder
30
comprises a viterbi data path
10
and a controller
20
. The data path
10
has an input buffer
12
, a symbol metric table (SMT) unit
13
, a branch metric unit
14
, an add compare select (ACS) unit
15
, a trace back unit
16
, and an output buffer
17
.
The controller
20
generates a variety of control signals CTL which are synchronized with a frame sync signal F_Sync. The viterbi data path
10
decodes a code sequence IN_DATA and outputs a decoded data OUT_DATA under the control of the control signals CTL from the controller
20
.
The control signals CTL synchronized with the frame synchronous signal F_Sync are also used for testing the viterbi decoder
30
, and thus the test time of the viterbi decoder
30
is determined and restricted by the frame synchronous signal F_Sync. In general, it takes about 12 ms (120,000 clock cycles with respect to 10 MHz clock) to test one frame with the control signals CTL synchronized with the frame sync signal F_Sync. Since several kinds of tests are normally needed to increase the test reliability of a viterbi decoder, a test time for one product increases in proportion to the numbers of the tests. Such features of a conventional viterbi decoder results in an increase in production cost.
In particular, for the scan-in/scan-out testing which is well known to those skilled in the art, many flip-flop circuits are needed to be constructed on the same chip on which a viterbi decoder is mounted. Hence, the viterbi decoder circuitry is complicated and requires a large amount of area, as a result, yielding an increase in production cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a viterbi decoder which performs enhanced test operations as well as normal operations, so that test time of the viterbi decoder may be shortened.
To attain the above object, a viterbi decoder according to the present invention comprises a plurality of buses for test control signals externally applied from a test system, a controller, a viterbi data path, and a test circuit. The controller generates a plurality of decoding control signals synchronized with a normal clock signal during a normal operation. The viterbi data path includes an input buffer, a symbol metric table unit, a branch metric unit, an add compare select unit, a trace back unit and an output buffer. The viterbi data path decodes code sequences provided from the test system. The viterbi data path is controlled by the decoding control signals from the controller, synchronizing with the normal clock signal during the normal operation.
The test circuit tests the controller and the viterbi data path with a plurality of test control signals and a test clock from the test system during a test operation. The test circuit comprises an address decoder which generates control signals for enabling other components of the viterbi decoder to perform the test. The test circuit receives from the test system address signals, a register write strobe signal, a register read strobe signal, a test mode selecting signal, and a normal mode selecting signal. The test circuit includes a test register for storing the test control signals and the code sequences in response to an enable signal from the address decoder and the test control signals, a first multiplexer which selects one of the normal clock and the test clock in response to a test clock enable signal from the test register, and a second multiplexer which selectively outputs either the decoding control signals from the controller or the test control signals from the test register in response to a test enable signal from the test register. The selected output signals of the second multiplexer are provided to the viterbi data path. The test circuit further includes a first buffer which outputs the output of the viterbi data path to the test system via the data bus in response to an enable signal from the address decoder, and a second buffer which outputs the output of the controller to the test system via the data bus in response to an enable signal from the address decoder.


REFERENCES:
patent: 4614933 (1986-09-01), Yamashita et al.
patent: 5710784 (1998-01-01), Kindred et al.
patent: 5737342 (1998-04-01), Ziperovich

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